Xavier integrates the core of cortex R5F, can all I/O be allocated to R5 for operation?

Xavier integrates the core of cortex R5F, can all I/O be allocated to R5 for operation?

What documents are there for reference? Thank you

Hello, aaron:
You mean SPE R5 core? You can download the source package from Jetson Download Center | NVIDIA Developer for corresponding SDK.
Generally, SPE R5 can only access those modules within AON cluster. You can check Xavier TRM for details about modules in AON.
In addition, there’s a doc folder in SPE firmware source package, which may help.

br
ChenJian