Hi, I’m trying to get ASM3142 chip working on Xavier NX. The chip is wired to USBSS and lanes 1 and 2 of PCIE0. Lanes 3 and 4 are unused. Otherwise the configuration is similar to the reference design. It appears that the PCIE0_RST remains pulled low (cannot yet verify what pulls it low, though) an…

Hello, Per checked this internally. This is not a bug. It is by design and the reason is that the C5 controller’s pex_rst and clkreq signals pinmux configuration registers are present in C5’s power domain and not in VDD_SOC. Since C5 is not unpowergated by the time MB1 comes into picture, MB1 can’…

Xavier NX and PCIE0 lane allocations, pinmux script inconsistency

Robotics & Edge Computing Jetson Systems Jetson Xavier NX

juho.roine January 8, 2021, 8:18am 25

Ok, thank you for the response.

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Xavier NX and PCIE0 lane allocations, pinmux script inconsistency

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