I’m trying to get ASM3142 chip working on Xavier NX. The chip is wired to USBSS and lanes 1 and 2 of PCIE0. Lanes 3 and 4 are unused. Otherwise the configuration is similar to the reference design. It appears that the PCIE0_RST remains pulled low (cannot yet verify what pulls it low, though) and dmesg says “tegra-pcie-dw 141a0000.pcie: PCIe link is not up…!”.
If the PCIE0 bus only occupies two lanes, does it need to be explicitly configured to that if other lanes are simply not used, and what is the correct way to do this on Xavier NX?
Some documents tell to set uphy-lane values and set UPHY_CONFIG to point to that file, but only such example config seems to be for p2972. There are num-lanes -values for the buses in devicetree, and those have been changed to 2 in the config. Anything else need to be configured?
One inconcistency got my attention in dts2cfg -script:
The excel pinmux-sheet exports the reset-pin as “pex_l5_rst_n” in pinmux DTSI file. However, the dts2cfg configuration (Linux_for_Tegra/kernel/pinmux/t19x/addr_info.txt) contains name “pex_l5_rst_n_pgg1” and therefore the script does not export this pin to pinmux.cfg. The similar applies to pin pex_l5_clkreq_n (pex_l5_clkreq_n_pgg0). Is this correct and does the pin really get initialized ok? I tried renaming pins in the excel exported file to get the configuration created, but it breaks the flashing procedure.
Does the pad voltage dtsi file (and corresponding dtb) have any role in actual initialization the hardware or is it just an intermediate file for .cfg file? Including the dtsi in the kernel device tree causes an error if any IO_PAD_VOLTAGE_OFF values exist.