About activating spi on jetson nano

Hello, @ShaneCCC

Another question for an old post.

Remove the TEGRA_GPIO B an B to try
I didn’t understand this part.

Do you mean to delete TEGRA_GPIO(BB, 0) below?
Are you telling me to delete TEGRA_GPIO(B, 4)?

Thank you.

Remove all of the (B, 4 5 6 7 group from the device tree if you stay in r32.6.x release.

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Hello, @ShaneCCC

**
**If I use R32.7.x, do I need to delete the above?
just from tegra210-porg-pinmux-p3448-0002-b00.dtsi
nvidia,pins = “spi1_mosi_pc0”;
nvidia,function = “spi1”;
nvidia,pin-label = “spi1_dout”;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;

Can I set it up as above?

Thank you.

No need for r32.7.x due to those context already removed for this release.

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Hello, @ShaneCCC

Then in R32.7.x, what kind of work is needed to activate spi?

Even if you set it like the link above

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | If you check grep -i spi, you will see something like this:

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
[sudo] password for manager:
Bank: 1 Reg: 0x70003050 Val: 0x0000e015 → spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e015 → spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e015 → spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e015 → spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e015 → spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006016 → spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006016 → spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006016 → spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006016 → spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006015 → spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 → spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 → spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 → spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 → spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002015 → qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002015 → qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002015 → qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002015 → qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002015 → qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002015 → qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 → drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 → drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 → drive_qspi_comp

Create dtb after kernel build

It was applied with FDT.

Can you also tell me how to make dtb to enable spi through NV_Jetson_Nano_Module_Pinmux_Config_Template.xlsm ?

Thank you.

You just need to run the jetson-io to configure the PINs for SPI.

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Hello, @ShaneCCC

I’m using jetson nano emmc module.

Thank you.

You need to modify the device tree like the reference topic you point out.

Thanks

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