AGX Orin Reset Clarification

[jayt121]

Hello,
Two questions regarding the SYS_RESET_N and PERIPH_RESET_N signals:

1. In the design guide, the pin descriptions for SYS_RESET_N and PERIPH_RESET_N both state that they do not affect the SoM’s power sequencer. The power block diagram, however, shows SYS_RESET_N going directly to the SoM’s power sequencing. Is the SoM power sequencing supposed to be affected by SYS_RESET_N?

2. In both the power block diagram and the pin description, PERIPH_RESET_N is shown to be AND’d with SYS_RESET_N which implies that PERIPH_RESET_N, by itself, shouldn’t have any effect on the SoM (unless it goes to other places not shown in the block diagram). Through testing we’ve shown that PERIPH_RESET_N does affect the SoM, but were looking for clarification on why it behaves differently than stated/shown in the block diagram.

   
   

[sgursal]

SYS_RESET_N is Bidirectional signal and PERIPHERAL_RESET_N is Input signal from the AGX Orin module perspective.

Please refer to 5.1 Power Sequencing section in the design guide.

[jayt121]

Hello sgursal - thank you for the reply.

I re-read section 5.1 of the design guide, but did not find answers or further clarification to what I posted above.

[sgursal]

SoM power sequencing is not affected by SYS_RESET_N from carrier board during power on.

PERIPH_RESET_N will reset the SOC, and memories on the module. It does not reset power sequencer.

Could you provide more details about your observations and UART logs if possible.