In our custom carrier board for AGX Xavier, we have a PC104e 3 bank connector.(https://en.wikipedia.org/wiki/PC/104). This has 4x1lane in one bank and 8xlane on other 2 banks. All PCIe lanes must share one reset line. Presently all reset lanes has independent reset lines in Xavier. We observe device connected to C5 (x8 lanes) fails to enumerate if we use reset line from C1 is shared for all devices. Using reset line from C5 will make all other device enumerations fail (This is expected, as C5 reset line is released after all other enumerations are completed.). Presently there is almost 1.2 seconds difference between C1 and C5 reset releases. Is there a way to use a common reset line for all PCIe interfaces ?