Common reset line for all PCIe

Hello,
In our custom carrier board for AGX Xavier, we have a PC104e 3 bank connector.(https://en.wikipedia.org/wiki/PC/104). This has 4x1lane in one bank and 8xlane on other 2 banks. All PCIe lanes must share one reset line. Presently all reset lanes has independent reset lines in Xavier. We observe device connected to C5 (x8 lanes) fails to enumerate if we use reset line from C1 is shared for all devices. Using reset line from C5 will make all other device enumerations fail (This is expected, as C5 reset line is released after all other enumerations are completed.). Presently there is almost 1.2 seconds difference between C1 and C5 reset releases. Is there a way to use a common reset line for all PCIe interfaces ?

Thanks,
Don.

I’m afraid this can’t be done. Each PCIe slot on Jetson-Xavier is owned by a different PCIe controller and hence different PERST# and CLKREQ# and REFCLK signals. So, using PERST# from a different controller is the wrong thing to do here.

Hello vidyas,

Thanks for the response.
Yes, We understand that each controller has separate signals. But this is a requirement of PC104e standard. DO you have any guess, why releasing reset early makes the enumeration fails ?
Could it be specific to end point ? We only have one device each to test this.

Thanks,
Don.

I’m still not clear on the topology here.
Do we have two endpoints here? Or only one endpoint? As I mentioned earlier, on Jetson-Xavier, one slot is owned by one controller and each slot has its own PERST#, CLKREQ#, REFCLK, and Tx/Rx lanes. If you are using PERST# from another controller, then, by the time the endpoint device observes a low->high transition on PERST#, it may not have REFCLK available. That could be one reason for the link not coming up.

Hello vidyas,

Attached are the block of PCIe lane distribution and schematic page of 3 bank connector.
There could be upto 4 x1 endpoints and one x8 end point. All have to share reset line.
We have some SBCs with intel SoCs. Intel have one PCIe reset line for all devices, so this was never a challenge there.

Thanks,
Don.




There could be upto 4 x1 endpoints and one x8 end point. All have to share reset line.
Why should they share the reset line? Where is this requirement coming from? AFAIU, this requirement is not compatible with PCIe specification’s requirement.
I mean, since 4 x1 endpoints are connected to C1 controller through a PCIe switch, it is logical for all four of them to receive reset signal from C1 and since x8 endpoint is connected to C5 controller, it should get its reset from C5.
Not only this, even the REFCLK to all 4 x1 controllers should be derived (directly or indirectly depending on the switch) from C1 and REFCLK of x8 endpoint should come from C5

Hello vidyas,

Thanks for the reply.

Why should they share the reset line? Where is this requirement coming from? AFAIU, this requirement is not compatible with PCIe specification’s requirement.

This is a requirement from PCIe104 standard. ( https://pc104.org/wp-content/uploads/2015/03/PCI104_Express_v3_0.pdf ). Search with PERST#.

Not only this, even the REFCLK to all 4 x1 controllers should be derived (directly or indirectly depending on the switch) from C1 and REFCLK of x8 endpoint should come from C5

Yes, connector provision for individual REFCLK.
Only thing to share is the PERST# signal.

Thanks,
Don.

It is weird that PCIe 104 has such a design. Unfortunately, we can’t support that with Tegra.