Configure mcp2515 on jetpack 5.02

I’m trying to get mcp2515 working using waveshares RS485 can hat, but I can send only one can frame before having bring can interface down and up again and cannot receive any can frames on Xavier NX. When I try to send several can messages I get error: write: No buffer space available, but dmesg doesn’t show any errors:
dmesg.log (67.0 KB)

Overlay file I used to configure device tree:
mcp251x-can-controller_overlay.dts (2.8 KB)

hello Aspor,

could you please refer to r35.1 developer guide to enable Controller Area Network (CAN).
https://docs.nvidia.com/jetson/archives/r35.1/DeveloperGuide/text/HR/ControllerAreaNetworkCan.html

That guide is about using onboard Time Triggered CAN and not about spi-can, so it’s mostly irrelevant. With JetPack 4.6.2 I could still use spi can. Have you disabled that functionality for some reason?

Or are you suggesting that I short mosi and miso pins to do loopback test? I can send one message to other device so it seems that wiring is done correctly.

It seems that driver in previous kernel had to be modified for gpio based interrupts: https://forums.developer.nvidia.com/t/jetson-nano-and-mcp2515-can-module/112271/24
Unfortunately that post had only build driver and not the source so I can’t use the patched driver with new jetpack version.

Are these modification still necessary? How can I enable gpio based interrupts for the driver?

Sorry for the late response, have you managed to get issue resolved or still need the support? Thanks

No I wasn’t able to solve the issue

After digging around documentation I found that jetpack 5.0.2 uses different numbering for gpio pins than 4.6, so I tried changing can interrupts from <0xc1 0x1> to <0x1e5 0x1> found with sudo cat /sys/kernel/debug/gpio | grep PY.01
After that i get error mcp251x spi0.0: failed to acquire irq 0 that i didn’t get before and now I cannot send even one can message.

After testing with jetpack 4.6 I got this overlay working. Now the question is what changes need to be done to get overlay working with jetpack 5.0.2?

mcp251x-can-controller_overlay_jetpack4_6.dts (3.0 KB)

hello Aspor,

you may modify the dtsi file with proper overlay information and a compatible string. please compile the sources to create *.dtbo file, and put it under /boot/ for Jetson-IO to recognize this file.
please refer to developer guide, To Create and Apply a DTB Overlay File as see-also.
thanks

Jetsoni-IO recognises while and I’m able to apply overlay to the device tree, but I cannot bring can interface up.

What is proper overlay information that i should modify the dtsi file with?
Can’t I use dtc to compile device tree files or do I need to compile whole kernel?

hello Aspor,

overlay it means overwrite the device tree property from the base.
so, you may use dtc utility to compile device tree directly without using overlay.

That’s not what I want. I want to have an overlay file that I can apply with jetson-io.py tool. There’s some documentation about this in here: Configuring the Jetson Expansion Headers — Jetson Linux<br/>Developer Guide 34.1 documentation but information feels limited.

I already have an overlay that works with L4T 32.7.2 but not with L4T 35.1. What I want to know is what changes are necessary to get the overlay working with L4T 35.1.

Here’s the overlay file:

/dts-v1/;
/plugin/;

/ {
	overlay-name = "MCP251x CAN Controller";
	compatible = "nvidia,p3449-0000+p3668-0000\0nvidia,p3509-0000+p3668-0000\0nvidia,tegra194";
	jetson-header-name = "Jetson 40pin Header";

   	fragment@0 {
		target-path = "/";
		__overlay__ {
			clocks {
				mcp251x_osc: mcp251x_osc{
                    status = "okay";
                    clock-output-names = "mcp251x_osc";
                    clock-accuracy = <0x64>;
                    clock-frequency = <0xb71b00>;
                    #clock-cells = <0x0>;
                    compatible = "fixed-clock";

				};
			};
		};
	};

    fragment@1 {
        target = <&pinmux>;
		__overlay__ {
            pinctrl-names = "default";
			pinctrl-0 = < &expheaderpinmux >;
			expheaderpinmux: exp-header-pinmux {
				hdr40-pin26 {
					nvidia,lpdr = <0x00>;
					nvidia,enable-input = <0x01>;
					nvidia,tristate = <0x00>;
					nvidia,pull = <0x02>;
					nvidia,function = "spi1";
					nvidia,pins = "spi1_cs1_pz7";
				};

				hdr40-pin24 {
					nvidia,lpdr = <0x00>;
					nvidia,enable-input = <0x01>;
					nvidia,tristate = <0x00>;
					nvidia,pull = <0x02>;
					nvidia,function = "spi1";
					nvidia,pins = "spi1_cs0_pz6";
				};

				hdr40-pin23 {
					nvidia,lpdr = <0x00>;
					nvidia,enable-input = <0x01>;
					nvidia,tristate = <0x00>;
					nvidia,pull = <0x01>;
					nvidia,function = "spi1";
					nvidia,pins = "spi1_sck_pz3";
				};



				hdr40-pin22 {
					nvidia,lpdr = <0x00>;
					nvidia,enable-input = <0x1>;
					nvidia,tristate = <0x0>;
					nvidia,pull = <0x2>;
					nvidia,function = "rsvd1";
					nvidia,pins = "spi3_miso_py1";
				};


				hdr40-pin21 {
					nvidia,lpdr = <0x00>;
					nvidia,enable-input = <0x01>;
					nvidia,tristate = <0x00>;
					nvidia,pull = <0x01>;
					nvidia,function = "spi1";
					nvidia,pins = "spi1_miso_pz4";
				};

				hdr40-pin19 {
					nvidia,lpdr = <0x00>;
					nvidia,enable-input = <0x01>;
					nvidia,tristate = <0x00>;
					nvidia,pull = <0x01>;
					nvidia,function = "spi1";
					nvidia,pins = "spi1_mosi_pz5";
				};
			};

		};
	};
	fragment@2 {
		target = <&spi0>;
		__overlay__ {
      nvidia,always-hw-cs;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			can@0{
				status = "okay";
				compatible = "microchip,mcp2515";
				reg = <0x0>;
				spi-max-frequency = <0x1e8480>;
				nvidia,rx-clk-tap-delay = <0x7>;
				clocks = <&mcp251x_osc>;
				interrupt-parent = <0x0c>;
				/*interrupt-parent = < &tegra_main_gpio>;/*
				interrupts = <0xc1 0x1>; /*gpio y1 pin 22 spi3_miso_py1> */
				controller-data {
                    nvidia,tx-clk-tap-delay = <0x0>;
                    nvidia,rx-clk-tap-delay = <0x1f>;
                    nvidia,cs-hold-clk-count = <0x1e>;
                    nvidia,cs-setup-clk-count = <0x1e>;
                    nvidia,enable-hw-based-cs;
				};
			};
		};
	};
};

I know that hdr40-pin22 nvidia,function needs to be something else than “rsvd1” because jetson-io.py won’t accept that value. But I don’t know what values are accepted and I cannot find documentation for nvidia,function. Value “spi3” is accepted by jetson-io.py but I’m not sure if it can be used for interrupt pin
I also belive that can@0 interrupts needs to be changed from <0xc1 0x1> to <0x1e5 0x1> but I haven’t got confirmation for this.
When I try these changes I get error: “mcp251x spi0.0: failed to acquire irq 0” in dmesg when I try to bring up can interface, so there’s still some errors in the dts file, but I cannot figure out what those errors are.

hello Aspor,

why don’t you refer to r35.1 public sources, it’s updated to match the new design of Jetson-IO tool.
the public sources package is available via https://developer.nvidia.com/embedded/jetson-linux-r351, please download [Driver Package (BSP) Sources] for checking.
$public_sources/kernel_src/hardware/nvidia/platform/tegra/common/kernel-dts/overlays/jetson-mcp251x.dts