CSI up to 3*4Lane or 4*4Lane?

Hello. nVidia

I am mailing to ask how many CSI-4lane communication simultaneously work?
Based on ‘3.2 Camera Expansion Header’ of document number SP-09778-001_V2.0 at page21, you are saying like ‘CSI up to 3*4 lane’. I think this means that three channels of CSI-4lane can work at the same time.
but Fig 3-1 right below upper expression at page 22 looks four channels of CSI-4lane work at the same time.
(4lane(1clk not used), 4lane(3clk not used), 4lane(5clk not used), 4lane(7clk not used), )
Which one is correct expression between comments at page21 and figure3-1 at page22?

What I want for my application is to use four channels of CSI-4lane run simultaneously. Is it possible? How do I do this?


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Please share the link of the doc SP-09778-001_V2.0 you got from.

For custom design, please refer to Design Guide in DLC. Jetson AGX Xavier supports four MIPI CSI x4 bricks.

The related link you asked me is as following.

Please, confirm which one is correct between the text 'CSI upto 34lane’ at page21 and CSI upto 44lane Fig 3-1 at page22.

Thanks in advance.

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The doc you mentioned is for devkit board only. For custom design you should refer to Design Guide as previous comment said. Jetson AGX Xavier supports four MIPI CSI x4 bricks.

And for the docs needed, please only refer to the official site: Jetson Download Center | NVIDIA Developer

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