eDP 10-bit support

Hello,

I want to use a Jetson TX2 module to drive a LCD module that have a 3840 x 2160 pixels with 10 bits RGB data input and 8 lanes eDP (4 lanes for one half on the screen and another 4 lanes for another half) with 2.7Gbps per lane. In the Jetson TX2 Module DataSheet v1.1 I found few points that in my opinion claim different thinks:

page 13:
"[i]Up to 36bpp* pixel depth on HDMI and DP; up to 24bpp* on DSI and eDP.

  • (Resolution + Refresh Rate + Pixel Depth + Format) must be within specification limits to achieve support for desired pixel depth.[/i]"
    where can I found description of those limits ?

page 32:
eDP is a mixed-signal interface consisting of 4 differential serial output lanes and 1 PLL. This PLL is used to generate a high frequency bit-clock from an input pixel clock enabling the ability to handle 10-bit parallel data per lane at the pixel rate for the desired mode. Embedded DisplayPort (eDP) modes (1.6GHz for RBR, 2.16GHz, 2.43GHz, 2.7GHz for HBR, 3.42GHz, 4.32GHz and 5.4GHz for HBR2).

page 33:
"[i]eDP 1.4

  • 1/2/4 lanes, single link
  • RBR/HBR/HBR2
    - 18/24/36 bit color depth
  • Up to 540 MHz
  • Internal panel: 4096 x 2160 @ 60Hz (2D – portrait/landscape); 1920 x 1080 @ 60Hz (3D – portrait/landscape)
  • -0.5% down spread support[/i]"

Maybe I’m missing somethin or mixed somethin up, but those information seems to be conflicted in the 10-bit resoluton area.

Hi,

Current valid values for color DEPTH are 8, 15, 16, 24bpp.

I guess you meant 10bpc, right? 30bpp is not yet supported in eDP.

Hi,

Yes, 10bpc so 30bpp. They are send as 8-bit data in such manner:

Lane0 - 
byte 1) Red1[9:2]
byte 2) Red1[1:0]+Green1[9:4]
byte 3) Green1[3:0]+Blue1[9:6]
byte 4) Blue1[5:0]+Red5[9:8]
byte 5) Red5[7:0]
byte 6) Green5[9:2]
byte 7) Green5[1:0]+Blue5[9:4]
byte 8) Clue5[3:0]+Red9[9:6]
...
Lane1 - 
byte 1) Red2[9:2]
byte 2) Red2[1:0]+Green2[9:4]
byte 3) Green2[3:0]+Blue2[9:6]
byte 4) Blue2[5:0]+Red6[9:8]
byte 5) Red6[7:0]
byte 6) Green6[9:2]
byte 7) Green6[1:0]+Blue6[9:4]
byte 8) Clue6[3:0]+Red10[9:6]
...
Lane2 - 
byte 1) Red3[9:2]
byte 2) Red3[1:0]+Green3[9:4]
byte 3) Green3[3:0]+Blue3[9:6]
byte 4) Blue3[5:0]+Red7[9:8]
byte 5) Red7[7:0]
byte 6) Green7[9:2]
byte 7) Green7[1:0]+Blue7[9:4]
byte 8) Clue7[3:0]+Red11[9:6]
...
Lane3 - 
byte 1) Red4[9:2]
byte 2) Red4[1:0]+Green4[9:4]
byte 3) Green4[3:0]+Blue4[9:6]
byte 4) Blue4[5:0]+Red8[9:8]
byte 5) Red8[7:0]
byte 6) Green8[9:2]
byte 7) Green8[1:0]+Blue8[9:4]
byte 8) Clue8[3:0]+Red12[9:6]
...

and the same on another 4 lanes but it starts from 1921 pixel.

So, the current version of Jetson TX2 don’t supports it ? Is it hardware or software limit ? Is there a possibility to make it work or is there not chance ?

It is a sw limit for X11. Since there was not much request for 10bit RGB, this does not support on TX2/TX1.

Ok, so do you have any suggestions how can I use jetson TX2 with this LCD ?

http://www.panelook.com/M320QAN01.0_AUO_32.0_LCM_overview_20790.html

Is it planned to support 30bpp ? What if I don’t use X11 ?

We provide OEM design guide, so that you can design eDP connector yourself.

https://developer.nvidia.com/embedded/dlc/jetson-tx2-oem-product-designguide

30bpp was discussed but still no plan yet. As for X11, if no X11 is used, there would be no mechanism to control current display mode.

I just checked TX2 TRM chapter 30 Display controller again. There is only 16,24,32bit RGB support from hardware.

Could you check that chapter and see is that what you want?
https://developer.nvidia.com/embedded/downloads Tegra X2 (Parker Series SoC) Technical Reference Manual

This document only confused me even more, cause inside mentioned section under “These color formats:” indeed there is no 30bpp.But if I understand this correctly, this section talks about the display controller that is used to every video output including also DP and HDMI. So in chapter 25 “Display interfaces: HDMI and DisplayPort” there is this:

25.2 Features (this is in section that talks about eDP,DP and HDMI)
[i]…
DP supports the following pixel depths:

  • 16 bpp RGB/YUV422
  • 18 bpp RGB/YUV444
  • 24 bpp RGB/YUV444
    - 30 bpp RGB/YUV444
  • 36 bpp RGB/YUV444
    …[/i]

25.3.1 Features (this is in section about eDP/DP)
[i]…

  • 18/24/36 bit color depth
    …[/i]

So, the DP and also HDMI seems to have no problem with 30bpp, is that correct ?
Anyway, I was thinking about using DP output and external converter to eDP, but before I’m gone do this, can you assure me that DP output will have no problem with 30bpp ?

Hi KZ,

Yes, from HW side, 30bpp is supported, but currently we don’t provide a SW pipeline to enable it.

It was a mistake to point out the display controller. Sorry for that. That is about input buffer format from multimedia pipeline.

So basically none of the available output (eDP, DP, HDMI, MIPI) currently support 30bpp and there is no near plan to enable it ?
DP and HDMI support 32bpp and eDP max 24bpp ? Is that correct ?

I think most is 24bpp RGB for DP,HDMI and eDP

Thanks for answers so far.

I just find out that nvidia shield tv is supporting 4K HDR and it is based on tegra X1, how come ? Does software that you use internally support it ?

You posted yester a link to this thered:
https://devtalk.nvidia.com/default/topic/1029229/jetson-tx2/is-it-possible-to-create-rgba-10-12-bit-egl-windows-and-frame-buffers-/

You deleted it because it is not relevant after all ?

Hi KZ,

Shield TV is not using L4T OS. The limitation here is on L4T but not kernel level. L4T has no HDR and YUV mode supported yet.

Yes, that topic is irrelevant.

Let’s give a last try.

Please add below under /etc/X11/xorg.conf

Section "Screen"
Identifier    "Default Screen"
Monitor        "Configured Monitor"
Device        "Configured Video Device"
DefaultDepth    30
EndSection

Thanks WayneWWW but I was in process of PCB design when I notice this conflicted information in documentation and ask about it, so I don’t have how to check it.

For now I will follow other thread that I mention, because I see that problem is the same and so as your recommend.