eDP Display Connection

I want to interface eDP Display b[/b] with TX1 board.
https://drive.google.com/open?id=0B8d7zQv-G71oTUVDVDdlU0JzNlk

For the same, we are designing one customized board daughter Interface which will connect to the Display expansion board of the TX1(J23).

Below are some questions,

  1. Our Display has 2 eDP Lanes, As per TX1’s JetsonTX1_Developer_Kit_Carrier_Board_Spec.pdf document, suggesting that we should use DP0_TX1 + & DP0_TX1 – for Lane 1 of the Display & DP0_TX2 + & DP0_TX2 – for Lane 0 of the display, Is it right connections?

  2. For eDP lines will Put 0.1uf, 10V in series of lines as suggested in TX1’s JetsonTX1_Developer_Kit_Carrier_Board_Spec.pdf document, any other special care need to be taken for the routing.

https://drive.google.com/open?id=0B8d7zQv-G71oellCRE55b0c3V28

  1. Can anyone please guide us if we need to put extra Capacitors or Pull-Ups on Power/Signal lines?

Hi RiteshPanchal,

  1. This connection in carrier board spec is wrong, will be updated in future, please take OEM DG (figure 19) as reference, that is: DP0_TX0 for lane 0 and DP0_TX1 for lane 1.

  2. 0.1uf is ok, please follow OEM DG to layout.

  3. No need other cap or pull-ups.

Thanks for the Reply.

Please find the block diagram we are planning. And also find the power ratings for eDP lanes, AUX, HPD.
https://drive.google.com/open?id=0B8d7zQv-G71oejQ2SlpPOEMwZUE

Below are some doubts,

  1. Do we need to add bi-directional level shifter for 1.8 to 3.3V, As our LCD VDD is 3.3V. If yes, Can you please suggest any level shifter IC or any general Purpose Level Shifter will work?
    As per datasheet of the LCD, it can operate between 3 to 3.6V and I think TX+/TX- can supply 1.8V only.

  2. Can we use VDD_3V3_SYS (coming from Pin # 61 & 63 of J23 in TX1 which has 3.3V) to the LCD_VCC as LCD needs 3.3V as supply? LCD Power Consumption is 1.15watt, will it able to supply these much of Power?

  3. Can we use VDD_SYS_BL (coming from Pin # 2,4,6, 8 of J23 inTX1 which has 19V ) to supply pin of Backlight of the LCD? Backlight Power Consumption is 2.45watt, will it able to supply these much of Power?

  4. Can we use VDD_3V3_SLP (coming from Pin # 16 of J23 in TX1) to the LCD_VCC? I think these will be shut off after the timeout period or if Module is in Deep Sleep so LCD will be turned off, correct?

  5. What is the use of LCD_RST_L coming from Pin # 12 of J23 of TX1?

I think one of your nVidia Colleague WayneWWW has interfaced AUO 14" 1080p eDP panel on v24.1 and v24.2 using E1824 Display board.

It would be great if you can share the schematic of E1824 Display board.
It will save a lot of time of us.

For 1, No need level shift for data lines as they are AC coupled, neither to AUX_CH lines as they are 1.8v/3.3v tolerant, only HPD needs level shift.

For 2 & 3, yes, no problem.

For 4, no, please don’t use it to LCD_VCC.

For 5, LCD_RST_L is only needed for panel that has such request.

Display board schematic is not public, OEM DG can cover most design requests.

hi,
I got my eDP display board as per your guideline.

I have given LCD_BL_EN to external fixed 3.3V. and LCD_BL_PWM to 5KHz 80% duty 3.3V pulse.
I got backlight ON.

For software i changed the extlinux.config like below,
FDT /boot/tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dtb

So, I am getting the following log

[    2.082192] tegradc tegradc.0: Display dc.54200000 registered with id=0
[    2.087904] of_dc_parse_platform_data: No dc-or-node is defined in DT
[    2.094459] display board info: id 0x0, fab 0x0
[    2.099439] display board info: id 0x0, fab 0x0
[    2.103777] of_dc_parse_platform_data: could not find vrr-settings node
[    2.109947] of_dc_parse_platform_data: nvidia,hdmi-vrr-caps not present
[    2.116508] of_dc_parse_platform_data: could not find cmu node for adobeRGB
[    2.123608] tegradc tegradc.0: DT parsed successfully
[    2.128725] tegradc tegradc.0: DSI: HS clock rate is 467500
[    2.200100] tegradc tegradc.0: nominal-pclk:155774000 parent:155773829 div:1.0 pclk:155773829 154216260~169793660
[    2.272770] tegradc tegradc.0: probed
[    2.354326] tegradc tegradc.0: nominal-pclk:155666000 parent:466996875 div:3.0 pclk:155665625 154109340~169675940
[    2.372409] Console: switching to colour frame buffer device 150x120
[    2.404765] tegradc tegradc.0: fb registered
[    2.409176] tegradc tegradc.1: Display dc.54240000 registered with id=1
[    2.415554] of_dc_parse_platform_data: No dc-or-node is defined in DT

So, i think my DISPLAY BOARD information is missing. (display board info: id 0x0, fab 0x0)
So what changes do in need to add in folloing files to enable AUO panel.

arch/arm/mach-tegra/board-panel.c
arch/arm64/boot/dts/tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dts
arch/arm/mach-tegra/panel-a-edp-1080p-14-0.c
arch/arm/mach-tegra/Makefile

And also my AUO panel is 1920x1200 and 10.1" instead of 1080p 14".

Issue seems resolved, see in https://devtalk.nvidia.com/default/topic/964977/jetson-tx1/enable-edp-on-tegradc-0-with-sor/post/5167364/#5167364