I tried to modify the tegra264-mb1-bct-pinmux-p3834-xxxx-p3971-0000-b02.dtsi file directly to enable SPI1(/dev/spidev0.0 ,810c590000.spi) , I was able to change nvidia,tristate from TEGRA_PIN_ENABLE to TEGRA_PIN_DISABLE, but I could not add nvidia,gpio-mode = <0x01> to the SPI1 pins (SCK, MOSI, MISO, CS0, CS1).
How can I add “nvidia,gpio-mode = <0x01>” to SPI1 without using jetson-io.py to apply the “jetson-io-hdr40-user-custom.dtbo” overlay?
Module: Thor T5000
Customized carrier board.
Conf: p3834-0008-p3971-0000-nvme.conf
Pinmux: tegra264-mb1-bct-pinmux-p3834-xxxx-p3971-0000-b02.dtsi
Pins of SPI1: spi1_sck_pj7,spi1_miso_pk0,spi1_mosi_pk1,spi1_cs0_pk2,spi1_cs1_pk3
Hi james_cheng1,
Have you confirmed that you are using p3971 rather than p4071 as the reference design for your custom carrier board?
We suggest using pinmux spreadsheet to generate the pinmux/gpio dtsi instead of updating them manually.
Yes, our carrier board references P3971_B02_Concept_schematics.pdf of Jetson AGX Thor Engineering Carrier Board Design Files (B02).zip.
I use the Jetson_Thor_Series_Modules_Pinmux_Template_v1.3.xlsm to generate the dtsi, and merge it to the tegra264-mb1-bct-pinmux-p3834-xxxx-p3971-0000-b02.dtsi, but it does not work.
Currently, I only can use default tegra264-mb1-bct-pinmux-p3834-xxxx-p3971-0000-b02.dtsi with overly jetson-io-hdr40-user-custom.dtbo to enable spi1.
AGX Thor devkit uses P4071 as carrier board.
I would suggest checking what’s the change in the generated pinmux/gpio dist after you configure the SPI1, and put those change into tegra264-mb1-bct-pinmux-p3834-xxxx-p3971-0000-b02.dtsi manually.
This DTBO is loaded in kernel rather than in early boot stage(i.e. MB1).