Flash failure on T5000 + customer design board

Robotics & Edge Computing Jetson Systems Jetson Thor
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1

Hi Nvidia,

I developed a board using the Jetpack 7 R38.2 SDK.
An error occurred during the flashing process. Why did the ‘BPMP firmware is not ready’ error occur?
Which step did I overlook? Please help!

flash cmd :
sudo ionice -c 1 -n 0 ./tools/kernel_flash/l4t_initrd_flash.sh --erase-all --flash-only --showlogs --network usb0 YY8-T5000 nvme0n1p1

flash_fail.txt (61.8 KB)
YY8-T5000.conf.txt (3.4 KB)

Thanks.

3

does this apply? pcie

4

Hi Whitesscott,

In my YY8-T5000.conf file, I used the following: ODMDATA=“uphy0-config-6,pcie@3_status=okay,uphy1-config-8”.

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image997×355 20.2 KB

I disabled PCIe C5 EP and disabled PCIe C4 EP in my kernel DTS configuration.

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image319×405 14.9 KB

PCIe C4 RP disabled and PCIe C5 RP enabled on source/hardware/nvidia/t264/nv-public/nv-platform/tegra264-p4071-0000.dtsi

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image352×264 11.1 KB

Thanks.

5

Hopefully, Nvidia will correct following where it’s incorrect.

Enable PCIe in a Customer CVB Design

# I don't think source/hardware/nvidia/t264/nv-public/nv-platform/tegra264-p4071-0000.dtsi gets compiled into a dtb.

# I think you have to edit kernel/dtb/tegra264-p4071-0000+p3834-0008-nv.dtb or bootloader/tegra264-p4071-0000+p3834-0008-nv.dtb

dtc -I dts -O dtb -o bootloader/tegra264-p4071-0000+p3834-0008-nv.dts \
    bootloader/tegra264-p4071-0000+p3834-0008-nv.dtb

# Make your pcie changes to tegra264-p4071-0000+p3834-0008-nv.dts 

Recompile it

 dtc -I dts -O dtb -o kernel_tegra264-p4071-0000+p3834-0008-nv.dtb \
    tegra264-p4071-0000+p3834-0008-nv.dtb

cp tegra264-p4071-0000+p3834-0008-nv.dtb bootloader/  OR kernel/dtb/
6

Hi pomelo_hsieh,

Is the issue specific to your custom carrier board?
If so, please share what’s the difference of the design on your custom carrier board(YY8-T5000)?

7

Hi Kevin,

1. yes

2. Unlike the Jetson Thor DevKit hardware design, the custom board utilizes the uphy0-config-6 and uphy1-config-8 configurations.

uphy0 Lane3 connect to PCIE SWITCH

uphy0 Lane6:7 connect to SSD

uphy1 Lane0:3 unused now

uphy1 Lane4:7 MGBE

I’m unsure if this experiment is valid.

Test on custom carrier board :

  1. Modified YY8-T5000.conf as follows:
    ODMDATA=“uphy0-config-6,pcie@3_status=okay,uphy1-config-8”;
    UPHY_CONFIG=“”;
    Flashing the image resulted in the error: tegra_bpmp_ipc_init_one: BPMP firmware is not ready

  2. However, directly modifying /bootloader/generic/tegra264-bpmp-3834-0008-4071-xxxx.dts and converting it back to /bootloader/generic/tegra264-bpmp-3834-0008-4071-xxxx.dtb avoids the “ERROR: tegra_bpmp_ipc_init_one: BPMP firmware is not ready” error.

I want to confirm whether using the ODMDATA method and directly modifying tegra264-bpmp-3834-0008-4071-xxxx.dtb will yield different results?
Or did I overlook a step during image generation that caused the settings not to be written?

Thanks.

8

This error indicates that ATF is waiting for BPMP-FW loaded but fails.
It may be caused from wrong BPMP-FW in use.

Please keep using direct BPMP DTB edits.

  1. Set uphy0-config = 6 and uphy1-config = 8 in tegra264-bpmp-3834-0008-4071-xxxx.dtb.
  2. Enable/disable pcie@3, MGBE speeds, etc. directly in that BPMP DTB.
    In the board conf only use ODMDATA:
ODMDATA="uphy0-config-6,pcie@3_status=okay";
UPHY_CONFIG="";

You can also verify with the latest Jetpack 7.1 GA(r38.4.0).