How can set the "BYPASS_LP_SEQ" and "T_HS_ZERO" at jeton TX1 R28.2?

How can set the “BYPASS_LP_SEQ” and “T_HS_ZERO” at jeton TX1 R28.2?
I can not find which file is define this.

hello sensor_test,

  1. may I have more details about why you need to configure the BYPASS_LP_SEQ?
    here’s definition of the BYPASS_LP_SEQ
sources/kernel/kernel-4.4/drivers/media/platform/tegra/camera/vi/registers.h
  1. about T_HS_ZERO, I think you mean the settle time for data lane moving from LP to HS.
    this is defined in the sensor device tree, ‘0’ means it would calculate automatically.
mode0 {
                                        ...
					cil_settletime = "0";

because the csi have then error
I think to change BYPASS_LP_SEQ and T_HS_ZERO to test it.

[ 1095.485342] vi 54080000.vi: tegra_channel_error_status:error 20022

hello sensor_test,

according to https://devtalk.nvidia.com/default/topic/1033195/jetson-tx1/what-is-the-tegra_channel_error_status-error-info-at-jetson-tx1-r28-2-/post/5256883/#5256883

you should co-work with your hardware engineer and checking this from the sensor side, to measure the mipi signaling is output correctly.