JetPack5.0.1 can not bring up on customer board

We use orin SOM on our customer board. After press power key, orin cannot bring up. The attached file is the log.
Please help to analyze.
not-boot-up.TXT (25.8 KB)

Your topic was posted in the wrong category. I am moving this to the Jetson AGX Orin category for visibility.

What’s the command you use to flash your Orin module?
Have device tree custom made for your carrier board?

Did you remember to change the cvb eeprom size in mb2 config?

Are you using different uphy config from devkit?

If you don’t know what I am talking about, share the diff between your hardware and the devkit.

Hi, kayccc:
(1) My flash command is : sudo ./ jetson-agx-orin-devkit mmcblk0p1
(2) I do not change anything to device tree and source code. With the same programmed orin SOM, DevKit can bring up, but our custom board can not bring up. The attached log is from our custom board.

Hi, WayneWWW:
I have deleted the following in Linux_for_Tegra/bootloader/tegra234-mb2-bct-common.dtsi :
// cvb_eeprom_i2c_instance = <0x0>;
// cvb_eeprom_i2c_slave_address = <0xac>;
//cvb_eeprom_read_size = <0x100>;

In addition, I have replace gpu.ko and Image in Linux_for_Tegra.

You didn’t answer the question at all. Please read my question again.

Hi, WayneWWW:
(1)Our hardware deleted eeprom, so I deleted the 3 lines in tegra234-mb2-bct-common.dtsi .
// cvb_eeprom_i2c_instance = <0x0>;
// cvb_eeprom_i2c_slave_address = <0xac>;
//cvb_eeprom_read_size = <0x100>;
(2)I did not change uphy config, ODMDATA is the same with DevKit.

So you also have MGBE on your board?

Yes, we have MGBE on our customer board.

FATAL ERROR [FILE=platform/drivers/uphy/uphy-tegra234.c, ERR_UID=2251]: start PLL 8 calibration failed

This means when BPMP-FW initializes GBE UPHY PLL2 (global PLL index=8), the external 156.25 MHz reference clock is not running.

If you still need MGBE on your custom board, then it means your platform requires MGBE and gbe-uphy-config is correct, but carrier board doesn’t enable the 156.25 MHz reference clock along with platform power-on.

How to enable the 156.25 MHz reference clock during power-on?

Please refer to the design guide document.

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