Hi NVIDIA Team,
I am working on a Jetson Orin Nano and need to configure PCIe C7 (pcie@141e0000) as PCIe Gen3 x1 for a PCIe-to-MAC device (LAN7431).
I found that the default C7 configuration in tegra234-p3768-0000.dtsi uses two lanes:
pcie@141e0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
phy-names = "p2u-0", "p2u-1";
};
However, NVIDIA already provides a C7 x1 configuration in:
board_config {
odm-data = "gbe-uphy-config-9";
};
pcie@141e0000 {
phys = <&p2u_gbe_0>;
phy-names = "p2u-0";
num-lanes = <1>;
};
I would like to clarify:
-
Do I need to create a separate/custom DT overlay for C7 x1, or can I use the existing gbe-uphy-config-9 configuration?
-
How can I confirm whether p3767-sku-handling-fragment@6 is actually being applied on my board?
-
Is the following configuration sufficient for C7 PCIe x1?
phys = <&p2u_gbe_0>;
phy-names = “p2u-0”;
num-lanes = <1>;
4 .Do I also need to set:
max-link-speed = <3>;
to use PCIe Gen3?
- Is any additional HSIO/UPHY or ODMDATA configuration required for C7 x1?
6.What is the recommended NVIDIA procedure for configuring C7 as PCIe Gen3 x1 without unnecessarily creating a duplicate overlay?
Your guidance on this as soon as your time permits would be incredibly helpful to keep our timeline on track.
Thank you.
Above one means if you set gbe-uphy-config-9 in your odmdata, then the following change would be applied. Thus, you only need to set odmdata to this one and no need to do anything else.
ODMDATA is defined in your board config.
Hi @WayneWWW ,
Currently used default (Default C7) connection for the NVMe SSD only. But we need to use 2 PCie from C7.
How do i configure C7 AND C9 SEPRATLEY SO, BOTH PCIE USED FOR DIFFERENT USECASES.??
We need to configure below things on seprate PCIe.
- x1(C7) : PCIE2_CLK, PCIE2_TX0, PCIE2_RX0
Planning to use this for NVMe SSD
- x1(C9) : PCIE3_CLK, PCIE2_TX1, PCIE2_RX1
Planning to use this for the PCIe to MAC-RGMII:: LAN7431T
Kindly provide details steps for above configuration (C7 and C9) and overlay file changes for above thing. We are using Nvidia Jetson Orin-Nano EVK.
-
Orin Nano devkit could not achieve C7+ C9 to run at same time because of hardware limitation.
-
The odmdata fragment already did the configuration… You don’t need to configure things but only ODMDATA.
Full code snippet..
109 p3767-sku-handling-fragment@6 {
110 target-path = "/bus@0";
111 board_config {
112 odm-data = "gbe-uphy-config-9";
113 };
114 __overlay__ {
115 /* C7 */
116 pcie@141e0000 {
117 phys = <&p2u_gbe_0>;
118 phy-names = "p2u-0";
119 num-lanes = <1>;
120 };
121
122 /* C9 */
123 pcie@140c0000 {
124 status = "okay";
125 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
126 phys = <&p2u_gbe_1>;
127 phy-names = "p2u-0";
128 num-lanes = <1>;
129 };
130 };
131 };
Hi,@WayneWWW From default C7 (where 2-lane configured for 1-clk) we need to run (C7) as 1 lane 1 clock and (C9) 1 lane 1 clock
so for that what overlay file changes we need to do?
Planning to use this for the PCIe to MAC-RGMII:: LAN7431T
What is the current default sw-configuration on NVIDIA Jetson orin Nano EVK configuration for this PCIe??
Default setting is PCIe C7 with 2 lanes on NV devkit.
These files are needed to get modified for enabling a PCIe
- Pinmux file
Pinmux file needs to updated for similar changes like this example.
- The kernel DT.
Kernel DT is actually not needed to get updated when you apply the correct ODMDATA to board config… as I already told twice.
You won’t be possible to use C9 on NV devkit. You have to made your own carrier board.
Hi, @WayneWWW how to apply ODMDATA in board config and where do we have to do it ? could you please provide the steps to configure these. As we will plan to use it in custom carrier board design. (All the changes and ODMDATA change configuration details)
We have checked below thing on NVIDIA Jetson Orin nano EVK and found below thing as default. As per below data it seems the C9 node is disbaled default on evk.
As in the board after running the command we can see the node
-------------------------------------------------------------
cat /proc/device-tree/bus@0/pcie@140c0000/status
disabled
cat /proc/device-tree/bus@0/pcie@141e0000/status
okay
The board config is the *.conf file under your Linux_for_Tegra directory.
That one in your flash command is the conf file you are using. That one has the ODMDATA.
We are using: GitHub - OE4T/tegra-demo-distro: Reference/demonstration distro for meta-tegra
hence, we are using yocto build for nvidia jetson orin nano and flashing using ./initrd.flash script in recovery mode.
kindly provide the details. thank you
Generally there is a “flashvars” file in yocto build and that one has the ODMDATA.
Again, please do not do this on Orin Nano devkit. It won’t work with default hardware.
Hi,@WayneWWW but IN “flashvars” file yocto build we don’t see anything like ODMDATA
okay as you said it wont work then what could be other way we can do ?
kindly provide the details. thank you
Is there a bpmp dtb defined in your flashvars?
If there is, then using dtc tool to convert back that bpmp dtb to dts. Modify that dts.
Below section could be modified
896 uphy {
897 status = "okay";
898 hsio-uphy-config = <0x00>;
899 hsstp-lane-map = <0x03>;
900 gbe-uphy-config = <0x08>;
901 };
Hi,@WayneWWW this is my “Flashvars” : 1 FLASHVARS="PMIC_CONFIG TBCDTB_FILE"
2 OVERLAY_DTB_FILE="tegra234-p3767-camera-p3768-fr_fpa_a_p22-overlay.dtbo,tegra234-p3767-camera-p3768-fr_imx900-cam0-2lane-overlay.dtbo,tegra234-p3767-camera-p3768-fr_i mx900-cam1-2lane-overlay.dtbo,tegra234-i2c6-dpaux-overlay.dtbo,tegra234-spi0-mcp2515-overlay.dtbo,tegra234-IF573-bluetooth-overlay.dtbo,tegra234-tmp112-overlay.dtbo,t egra234-sht40-overlay.dtbo,tegra234-pcie-c7-x1-overlay.dtbo"
3 CHIPID=0x23
4 PLUGIN_MANAGER_OVERLAYS="tegra234-carveouts.dtbo,tegra-optee.dtbo,tegra234-p3768-0000+p3767-0000-dynamic.dtbo,tegra234-p3767-camera-p3768-imx219-dual.dtbo,tegra234-i2 c6-dpaux-overlay.dtbo,tegra234-spi0-mcp2515-overlay.dtbo,tegra234-IF573-bluetooth-overlay.dtbo,tegra234-tmp112-overlay.dtbo,tegra234-sht40-overlay.dtbo,tegra234-pcie- c7-x1-overlay.dtbo"
5 BPFDTB_FILE="tegra234-bpmp-3767-0003-3768-super.dtb"
6 BPF_FILE="bpmp_t234-TE950M-A1_prod.bin"
7 BR_CMD_CONFIG="tegra234-mb1-bct-reset-p3767-0000.dts"
8 CHIP_SKU="00:00:00:D5"
9 DEVICEPROD_CONFIG="tegra234-mb1-bct-cprod-p3767-0000.dts"
10 DEVICE_CONFIG="tegra234-mb1-bct-device-p3767-0000.dts"
11 DEV_PARAMS="tegra234-br-bct-p3767-0000-l4t.dts"
12 DEV_PARAMS_B="tegra234-br-bct_b-p3767-0000-l4t.dts"
13 EMC_FUSE_DEV_PARAMS="tegra234-br-bct-diag-boot.dts"
14 GPIOINT_CONFIG="tegra234-mb1-bct-gpioint-p3767-0000.dts"
15 MB2BCT_CFG="tegra234-mb2-bct-misc-p3767-0000.dts"
16 MINRATCHET_CONFIG="--minratchet_config tegra234-mb1-bct-ratchet-p3767-0000.dts"
17 MISC_CONFIG="tegra234-mb1-bct-misc-p3767-0000.dts"
18 PINMUX_CONFIG="tegra234-pinmux.dtsi"
19 PMC_CONFIG="tegra234-padvoltage-default.dtsi"
20 PMIC_CONFIG="tegra234-mb1-bct-pmic-p3767-0000-@PMICREV@.dts"
21 PROD_CONFIG="tegra234-mb1-bct-prod-p3767-0000.dts"
22 SCR_CONFIG="tegra234-mb2-bct-scr-p3767-0000.dts"
23 TBCDTB_FILE="@DTBFILE@"
24 UPHY_CONFIG="--uphy tegra234-mb1-bct-uphylane-si.dtsi"
25 WB0SDRAM_BCT="tegra234-p3767-0001-wb0sdram-l4t.dts"
26 CHECK_BOARDID="3767"
27 CHECK_BOARDSKU="0005"
28 BOOTCONTROL_OVERLAYS="L4TConfiguration.dtbo,L4TConfiguration-RootfsRedundancyLevelABEnable.dtbo"
From above flashvars could you please guide is there anything ? thank you .
Hi , @WayneWWW Just wanted to show before editing 5 BPFDTB_FILE=“tegra234-bpmp-3767-0003-3768-super.dtb” that we have done this configuration in the overlay for 1 lane :
so kindly take a look once and guide us if anything is wrong
and the change in this : 5 BPFDTB_FILE=“tegra234-bpmp-3767-0003-3768-super.dtb” what and how will it affect?
/dts-v1/;
/plugin/;
/ {
overlay-name = "C4 PCIe Gen3 x4 LAN7431T";
compatible =
"nvidia,p3768-0000+p3767-0000",
"nvidia,p3768-0000+p3767-0001",
"nvidia,p3768-0000+p3767-0003",
"nvidia,p3768-0000+p3767-0004",
"nvidia,p3768-0000+p3767-0005",
"nvidia,p3768-0000+p3767-0000-super",
"nvidia,p3768-0000+p3767-0001-super",
"nvidia,p3768-0000+p3767-0003-super",
"nvidia,p3768-0000+p3767-0004-super",
"nvidia,p3768-0000+p3767-0005-super",
"nvidia,p3509-0000+p3767-0000",
"nvidia,p3509-0000+p3767-0001",
"nvidia,p3509-0000+p3767-0003",
"nvidia,p3509-0000+p3767-0004",
"nvidia,p3509-0000+p3767-0005";
fragment@0 {
target-path = "/bus@0/pcie@14160000";
__overlay__ {
status = "okay";
num-lanes = <1>;
max-link-speed = <3>;
};
};
};
but still when we run command lscpi -vv we still find the default Realtek one
the lanes are also configured as 1 lane as you can check from below
our .ko is also in board
Thank You.
What is the purpose of your kernel change here?
Bpmp dtb change will enable your PCIe C7 to just one lane and also PCIe C9 will be enabled… If you don’t change bpmp dtb, then it will always be C7 only with x2 setting.
And what I asked you to do in bpmp dtb is already mentioned in previous comment.
Just to clarify. I don’t see any reason to modify PCIe C4 setting here.
The default setting is already a good one. The max speed is gen 3 for Orin Nano by default. And whether it is x4 or x1 does not really matter. Changing that setting only has chance to make your card not able to get enumerted. Please just keep it as default one.
Also, this topic is only for PCIe C7, pleaes do not bring any other new items into this. You could create new topic for those unrelated items. Though I don’t see anything you need to do in PCIe C4.
