How do I know what the current core clock speed of the Jetson Sensor Processing Engine (SPE) is?
How do I set the SPE’s core clock speed to 200Mhz?
My hardware platform is TX2-NX, software version is L4T-R32.7.3
Hello,
SPE clock is fixed, and no need to set or change.
br
ChenJian
Hello Chenjian,
Is the current SPE clock 200Mhz?
Hello,
Sorry for delayed response. Different chips/SKUs may have different settings.
I have no TX2NX in hand.
Can you try the following command to check?
in
/sys/kernel/debug/bpmp/debug/clk/aon_cpu_nic
cat rate
cat possible_parents
cat parent
Different clock parent may result in different clock.
br
ChenJian
Hello ChenJian,
I used the command you gave to query and got the following results：
Does this mean its system clock frequency is 19.2Mhz?
Please try to change the parent to other sources, like
echo pll_p_out0 > parent
br
ChenJian
Hello ChenJian,
I used the “echo pll_p_out0 > parent” command and got the new clock frequency，Does this mean that the SPE system clock has been switched to 204Mhz?
Hello ChenJian,
If this means that the system clock of the SPE has been switched to 204Mhz, then how do I fix this frequency when booting? Do I need to modify the bpmp device tree?
Hi easyzoom,
Please share your bpmp dtb as file here for further check.
Please decompile the dtb and modify the following line in dts
- aon_cpu = <0xd0 0x264 0x249f000 0x1>;
+ aon_cpu = <0xd0 0x10d 0xc28cb00 0x1>;
and then assemble it back to dtb.
After re-flashing the board, it would apply to use pll_out0 as parent clock by default.
Hi，
I tried it, and it didn’t change the system clock speed of spe.
What’s your parent clock and rate for aon_cpu_nic before and after you apply above change I shared?
Hi，
Although 204Mhz is shown here, I feel that it is not that high a frequency because freertos-common/code-common/tegra-can.c:307 [mttcan_tx_complete] “No Tx completion ack received” error is always reported.
Is the current result the same as you configure them in runtime?
Could you share the full dmesg for further check?
What’s your current use case?
1.“echo pll_p_out0 > parent” has indeed been modified
2.freertos-common/code-common/tegra-can.c:307 [mttcan_tx_complete] “No Tx completion ack received” error is output on the serial port of spe. nothing prints in dmesg
3.I enabled the mttcan function of spe through mttcan<->spe-fw<->linux
Hello, easyzoom:
Once you confirmed that the SPE clock is working as expected, we can close this thread.
Regarding to
freertos-common/code-common/tegra-can.c:307 [mttcan_tx_complete] “No Tx completion ack received” error is output on the serial port of spe
You can file a new thread. That should be related to SPE firmware development.
CAN test in TX2 has been verified before. Have you ever mounted CAN transceiver?
br
Chenjian
Okay, I will mention a new discussion about the can part
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