Kernel recognizes dsi display, but cboot does not, cannot show bootlogo

Hello I am working with a display that the kernel seems to recognize and i can see my application GUI, but for some reason Cboot says that it is not supported, I know that Cboot for nano is closed sourced, but was hoping to understand why exactly is it happening and if is there a solution.
I think that my host1x display device tree part is loaded at the end of Uboot and in the kernel and not from Cboot.
Why would that be the case? any hints will be appreciated.

Device tree file and serial log are uploaded
minicom.cap (62.2 KB)
tegra210-p3448-0002-p3449-0000-b00.dts (18.5 KB)
for complete reference

Cboot and Uboot log

[0002.314] Welcome to L4T Cboot
[0002.317] 
[0002.318] Cboot Version: 00.00.2018.01-t210-39562017
[0002.323] calling constructors
[0002.326] initializing heap
[0002.329] initializing threads
[0002.332] initializing timers
[0002.335] creating bootstrap completion thread
[0002.339] top of bootstrap2()
[0002.342] CPU: ARM Cortex A57
[0002.345] CPU: MIDR: 0x411FD071, MPIDR: 0x80000000
[0002.350] initializing platform
[0002.404] Config for emmc ddr50 mode completed
[0002.408] sdmmc bdev is already initialized
[0002.412] Enable APE clock
[0002.415] Un-powergate APE partition
[0002.418] of_register: registering tegra_udc to of_hal
[0002.423] of_register: registering inv20628-driver to of_hal
[0002.429] of_register: registering ads1015-driver to of_hal
[0002.435] of_register: registering lp8557-bl-driver to of_hal
[0002.440] of_register: registering bq2419x_charger to of_hal
[0002.446] of_register: registering bq27441_fuel_gauge to of_hal
[0002.458] gpio framework initialized
[0002.461] of_register: registering tca9539_gpio to of_hal
[0002.466] of_register: registering tca9539_gpio to of_hal
[0002.472] of_register: registering i2c_bus_driver to of_hal
[0002.477] of_register: registering i2c_bus_driver to of_hal
[0002.483] of_register: registering i2c_bus_driver to of_hal
[0002.488] pmic framework initialized
[0002.492] of_register: registering max77620_pmic to of_hal
[0002.497] regulator framework initialized
[0002.501] of_register: registering tps65132_bl_driver to of_hal
[0002.507] initializing target
[0002.513] gpio_driver_register: register 'tegra_gpio_driver' driver
[0002.524] fixed regulator driver initialized
[0002.542] initializing OF layer
[0002.545] NCK carveout not present
[0002.548] Skipping dts_overrides
[0002.552] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
[0002.570] I2C Bus Init done
[0002.573] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
[0002.583] I2C Bus Init done
[0002.586] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
[0002.596] I2C Bus Init done
[0002.599] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
[0002.609] I2C Bus Init done
[0002.612] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
[0002.622] I2C Bus Init done
[0002.625] of_children_init: Ops found for compatible string maxim,max77620
[0002.635] max77620_init using irq 118
[0002.640] register 'maxim,max77620' pmic
[0002.645] gpio_driver_register: register 'max77620-gpio' driver
[0002.651] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
[0002.661] I2C Bus Init done
[0002.665] NCK carveout not present
[0002.675] Find /i2c@7000c000's alias i2c0
[0002.679] get eeprom at 1-a0, size 256, type 0
[0002.688] Find /i2c@7000c500's alias i2c2
[0002.692] get eeprom at 3-a0, size 256, type 0
[0002.696] get eeprom at 3-ae, size 256, type 0
[0002.701] pm_ids_update: Updating 1,a0, size 256, type 0
[0002.706] I2C slave not started
[0002.709] I2C write failed
[0002.712] Writing offset failed
[0002.715] eeprom_init: EEPROM read failed
[0002.719] pm_ids_update: eeprom init failed
[0002.723] pm_ids_update: Updating 3,a0, size 256, type 0
[0002.753] pm_ids_update: The pm board id is 3448-0002-400
[0002.760] Adding plugin-manager/ids/3448-0002-400=/i2c@7000c500:module@0x50
[0002.768] pm_ids_update: pm id update successful
[0002.773] pm_ids_update: Updating 3,ae, size 256, type 0
[0002.778] I2C slave not started
[0002.781] I2C write failed
[0002.784] Writing offset failed
[0002.787] eeprom_init: EEPROM read failed
[0002.791] pm_ids_update: eeprom init failed
[0002.821] eeprom_get_mac: EEPROM invalid MAC address (all 0xff)
[0002.827] shim_eeprom_update_mac:267: Failed to update 0 MAC address in DTB
[0002.834] eeprom_get_mac: EEPROM invalid MAC address (all 0xff)
[0002.840] shim_eeprom_update_mac:267: Failed to update 1 MAC address in DTB
[0002.849] updating /chosen/nvidia,ethernet-mac node 00:04:4b:e9:f3:82
[0002.855] Plugin Manager: Parse ODM data 0x000a4000
[0002.868] shim_cmdline_install: /chosen/bootargs: console=ttyS0,115200 console=tty0 fbcon=map:0 net 
[0002.888] Find /i2c@7000c000's alias i2c0
[0002.891] get eeprom at 1-a0, size 256, type 0
[0002.901] Find /i2c@7000c500's alias i2c2
[0002.904] get eeprom at 3-a0, size 256, type 0
[0002.909] get eeprom at 3-ae, size 256, type 0
[0002.913] pm_ids_update: Updating 1,a0, size 256, type 0
[0002.919] I2C slave not started
[0002.922] I2C write failed
[0002.924] Writing offset failed
[0002.927] eeprom_init: EEPROM read failed
[0002.931] pm_ids_update: eeprom init failed
[0002.935] pm_ids_update: Updating 3,a0, size 256, type 0
[0002.965] pm_ids_update: The pm board id is 3448-0002-400
[0002.972] Adding plugin-manager/ids/3448-0002-400=/i2c@7000c500:module@0x50
[0002.979] pm_ids_update: pm id update successful
[0002.983] pm_ids_update: Updating 3,ae, size 256, type 0
[0002.989] I2C slave not started
[0002.991] I2C write failed
[0002.994] Writing offset failed
[0002.997] eeprom_init: EEPROM read failed
[0003.001] pm_ids_update: eeprom init failed
[0003.031] Add serial number:1423219011007 as DT property
[0003.039] Applying platform configs
[0003.046] platform-init is not present. Skipping
[0003.050] calling apps_init()
[0003.072] Found 19 GPT partitions in "sdmmc3_user"
[0003.076] Proceeding to Cold Boot
[0003.079] starting app android_boot_app
[0003.083] Device state: unlocked
[0003.086] display console init
[0003.095] could not find regulator
[0003.118] hdmi cable not connected
[0003.121] is_hdmi_needed: HDMI not conDT entry for leds-pwm not found
n[0003.131] ected, returning false
[0003.134] hdmi is not connected
[0003.139] Panel: a,wxga-8-0 **<-- here is the display**
[0003.141] Unsupported panel **<-- why unsupported?**
[0003.144] display_console_init: no valid display out_type
[0003.152] subnode volume_up is not found !
[0003.156] subnode back is not found !
[0003.160] subnode volume_down is not found !
[0003.164] subnode menu is not found !
[0003.168] Gpio keyboard init success
[0003.216] found decompressor handler: lz4-legacy
[0003.231] decompressing blob (type 1)...
[0003.289] display_resolution: No display init
[0003.293] Failed to retrieve display resolution
[0003.298] Could not load/initialize BMP blob...ignoring
[0003.348] decompressor handler not found
[0003.352] load_firmware_blob: Firmware blob loaded, entries=2
[0003.358] XUSB blob version 0 size 124416 @ 0x92cb428c
[0003.364] -------> se_aes_verify_sbk_clear: 747
[0003.368] se_aes_verify_sbk_clear: Error
[0003.372] SE operation failed
[0003.375] bl_battery_charging: connected to external power supply
[0003.384] display_console_ioctl: No display init
[0003.388] switch_backlight failed
[0003.398] device_query_partition_size: failed to open partition sdmmc3_user:MSC !
[0003.405] MSC Partition not found
[0003.415] device_query_partition_size: failed to open partition sdmmc3_user:USP !
[0003.422] USP partition read failed!
[0003.426] blob_init: blob-partition USP header read failed
[0003.431] android_boot Unable to update recovery partition
[0003.437] kfs_getpartname: name = LNX
[0003.440] Loading kernel from LNX
[0003.526] load kernel from storage
[0003.536] decompressor handler not found
[0003.556] Successfully loaded kernel and ramdisk images
[0003.561] board ID = D78, board SKU = 2
[0003.566] display_resolution: No display init
[0003.570] Failed to retrieve display resolution
[0003.574] bmp blob is not loaded and initialized
[0003.579] Failed to display boot-logo
[0003.583] NCK carveout not present
[0003.586] Skipping dts_overrides
[0003.589] NCK carveout not present
[0003.599] Find /i2c@7000c000's alias i2c0
[0003.603] get eeprom at 1-a0, size 256, type 0
[0003.612] Find /i2c@7000c500's alias i2c2
[0003.616] get eeprom at 3-a0, size 256, type 0
[0003.620] get eeprom at 3-ae, size 256, type 0
[0003.625] pm_ids_update: Updating 1,a0, size 256, type 0
[0003.630] I2C slave not started
[0003.633] I2C write failed
[0003.636] Writing offset failed
[0003.639] eeprom_init: EEPROM read failed
[0003.643] pm_ids_update: eeprom init failed
[0003.647] pm_ids_update: Updating 3,a0, size 256, type 0
[0003.677] pm_ids_update: The pm board id is 3448-0002-400
[0003.684] Adding plugin-manager/ids/3448-0002-400=/i2c@7000c500:module@0x50
[0003.692] pm_ids_update: pm id update successful
[0003.697] pm_ids_update: Updating 3,ae, size 256, type 0
[0003.702] I2C slave not started
[0003.705] I2C write failed
[0003.708] Writing offset failed
[0003.711] eeprom_init: EEPROM read failed
[0003.715] pm_ids_update: eeprom init failed
[0003.745] eeprom_get_mac: EEPROM invalid MAC address (all 0xff)
[0003.751] shim_eeprom_update_mac:267: Failed to update 0 MAC address in DTB
[0003.759] eeprom_get_mac: EEPROM invalid MAC address (all 0xff)
[0003.764] shim_eeprom_update_mac:267: Failed to update 1 MAC address in DTB
[0003.773] updating /chosen/nvidia,ethernet-mac node 00:04:4b:e9:f3:82
[0003.779] Plugin Manager: Parse ODM data 0x000a4000
[0003.792] shim_cmdline_install: /chosen/bootargs: console=ttyS0,115200 console=tty0 fbcon=map:0 net 
[0003.805] Add serial number:1423219011007 as DT property
[0003.814] "bpmp" doesn't exist, creating 
[0003.820] Updated bpmp info to DTB
[0003.825] Updated initrd info to DTB
[0003.828] "proc-board" doesn't exist, creating 
[0003.834] Updated board info to DTB
[0003.838] "pmu-board" doesn't exist, creating 
[0003.844] Updated board info to DTB
[0003.847] "display-board" doesn't exist, creating 
[0003.853] Updated board info to DTB
[0003.857] "reset" doesn't exist, creating 
[0003.861] Updated reset info to DTB
[0003.865] display_console_ioctl: No display init
[0003.869] display_console_ioctl: No display init
[0003.874] display_console_ioctl: No display init
[0003.878] Cmdline: tegraid=21.1.2.0.0 ddr_die=4096M@2048M section=512M memtype=0 vpr_resize usb_por 
[0003.913] DTB cmdline: console=ttyS0,115200 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_b 
[0003.924] Updated bootarg info to DTB
[0003.928] Adding uuid 000000016445b5081400000018ff0080 to DT
[0003.934] Adding eks info 0 to DT
[0003.939] WARNING: Failed to pass NS DRAM ranges to TOS, err: -7
[0003.945] Updated memory info to DTB
[0003.953] set vdd_core voltage to 1075 mv
[0003.957] setting 'vdd-core' regulator to 1075000 micro volts
[0003.963] Found secure-pmc; disable BPMP


U-Boot 2021.01 (Jul 31 2021 - 13:53:18 +0000)

SoC: tegra210
Model: NVIDIA Jetson Nano Developer Kit
Board: NVIDIA P3450-0002
DRAM:  4 GiB
MMC:   sdhci@700b0000: 1, sdhci@700b0600: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Hit any key to stop autoboot:  0 
Retrieving file: /boot/extlinux/extlinux.conf
205 bytes read in 15 ms (12.7 KiB/s)
1:      my-Linux
Retrieving file: /boot/extlinux/../initrd
2096919 bytes read in 65 ms (30.8 MiB/s)
Retrieving file: /boot/extlinux/../Image
35567624 bytes read in 840 ms (40.4 MiB/s)
append: tegraid=21.1.2.0.0 ddr_die=4096M@2048M section=512M memtype=0 vpr_resize usb_port_owner_info 
Moving Image from 0x84000000 to 0x84080000, end=86308000
## Flattened Device Tree blob at 83100000
   Booting using the fdt blob at 0x83100000
ERROR: reserving fdt memory region failed (addr=0 size=0)
ERROR: reserving fdt memory region failed (addr=0 size=0)
   Using Device Tree in place at 0000000083100000, end 0000000083182863
copying carveout for /host1x@50000000/dc@54200000...  **<-- here is the device tree definition  for the DSI **
copying carveout for /host1x@50000000/dc@54240000... **<-- here is the device tree definition for the DSI  why**

Starting kernel ...

Kernel log

tegradc tegradc.1: disp0 connected to head1->/host1x/dsi
[    0.877049] display board info: id 0x0, fab 0x0
[    0.877094] tegra_cec 70015000.tegra_cec: cec_add_sysfs ret=0
[    0.877113] tegra_cec 70015000.tegra_cec: probed
[    0.877285] tegradc tegradc.1: No hpd-gpio in DT
[    0.877395] tegradc tegradc.1: DT parsed successfully
[    0.877463] tegradc tegradc.1: Display dc.ffffff800acc0000 registered with id=0
[    0.879179] of_fixed_clk: probe of can_clock failed with error -17
[    0.879187] tegradc tegradc.1: prod settings missing -19
[    0.879387] tegra-pcie 1003000.pcie: PCI host bridge to bus 0000:00
[    0.879408] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    0.879424] pci_bus 0000:00: root bus resource [mem 0x13000000-0x1fffffff]
[    0.879435] tegradc tegradc.1: pad_ab_default not found -19
[    0.879440] tegradc tegradc.1: pad_ab_idle not found -19
[    0.879443] tegradc tegradc.1: pad_cd_default not found -19
[    0.879446] tegradc tegradc.1: pad_cd_idle not found -19
[    0.879481] pci_bus 0000:00: root bus resource [mem 0x20000000-0x3fffffff pref]
[    0.879502] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.879815] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.880766] tegradc tegradc.1: probed
[    0.881201] Console: switching to colour frame buffer device 60x50
[    0.881238] tegradc tegradc.1: fb registered
    0.883600] tegra-apbdma 60020000.dma: Tegra20 APB DMA driver register 32 channels
[    0.887852] tegra-adma 702e2000.adma: Tegra210 ADMA driver registered 22 channels
[    0.888245] tegra-fuse-burn 7000f800.efuse:efuse-burn: shutdown limit check disabled
[    0.888261] tegra-fuse-burn 7000f800.efuse:efuse-burn: Fuse burn driver initialized
[    0.888475] kfuse 7000fc00.kfuse: initialized
[    0.889039] tegra-pmc-iopower pmc-iopower: Regulator supply iopower-dbg-supply not available
[    0.889724] tegra-pmc-iopower pmc-iopower: NO_IOPOWER setting 0x0
[    0.890355] tegra-dfll-pwm 70110000.pwm: DFLL_PWM regulator is available now
[    0.890372] vdd-cpu: 708 <--> 1322 mV at 708 mV 
[    0.890679] pwm-regulator pwm_regulators:pwm-regulator@0: PWM regulator registration passed
[    0.890881] pci 0000:00:01.0: BAR 14: assigned [mem 0x13000000-0x130fffff]
[    0.890901] pci 0000:01:00.0: BAR 0: assigned [mem 0x13000000-0x13003fff 64bit]
[    0.890927] pci 0000:00:01.0: PCI bridge to [bus 01]
[    0.890940] pci 0000:00:01.0:   bridge window [mem 0x13000000-0x130fffff]
[    0.891216] pcieport 0000:00:01.0: Signaling PME through PCIe PME interrupt
[    0.891232] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
[    0.891802] vdd-gpu: applied init 1000000uV constraint
[    0.891817] vdd-gpu: 708 <--> 1323 mV at 997 mV 
[    0.892142] pwm-regulator pwm_regulators:pwm-regulator@1: PWM regulator registration passed
[    0.895004] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.895079] No Device Node present for smmu client: serial8250 !!
[    0.895095] platform serial8250: No iommus property found in DT node, got swgids from fixup(10100)
[    0.895128] iommu: Adding device serial8250 to group 33
[    0.896548] console [ttyS0] disabled
[    0.896602] 70006000.serial: ttyS0 at MMIO 0x70006000 (irq = 62, base_baud = 25500000) is a Tegra
[    1.184419] tegradc tegradc.1: nominal-pclk:29448000 parent:29447753 div:1.0 pclk:29447753 2915350
[    1.184989] tegradc tegradc.1: DSI: HS clock rate is 204500
[    1.898792] tegra_cec 70015000.tegra_cec: Can't find physical addresse.
[    1.898796] tegra_cec 70015000.tegra_cec: tegra_cec_init Done.
[    3.248685] console [ttyS0] enabled
[    3.252907] 70006040.serial: ttyTHS1 at MMIO 0x70006040 (irq = 63, base_baud = 0) is a TEGRA_UART

Device tree, dtb file tegra210-p3448-0002-p3449-0000-b00.dts

host1x {
		dc@54200000 {
			status = "disabled"; 
		};
		/* DSI mapped to tegradc.1 */
		dc@54240000 {
			status = "okay";
			nvida,dc-or-node = "/host1x/dsi";
			nvidia,dc-connector = <&dsi>;
			// DSI supplies 
			avdd_dsi_csi-supply = <&max77620_sd3>;
			avdd_lcd-supply = <&battery_reg>;
			dvdd_lcd-supply = <&battery_reg>;
			vdd_lcd_bl_en-supply = <&battery_reg>;
			vdd_lcd_bl-supply = <&battery_reg>;
			
		};
		/*
		h_ref_to_sync and v_ref_to_sync is used by nv driver only. You have to put proper value to meet the constraint in our driver.

		Please refer to mode.c -> check_ref_to_sync() for the constraint.
		nvidia,dsi-init-cmd: panel required init command sequence.
		nvidia,dsi-n-init-cmd: command counts of init command sequence, including delay set.
		nvidia,dsi-suspend-cmd: panel required suspend command sequence.
		nvidia,dsi-n-suspend-cmd: command counts of suspend command sequence, including delay set.
		nvidia,dsi-early-suspend-cmd: panel required early suspend command sequence.
		nvidia,dsi-n-early-suspend-cmd: command counts of early suspend command sequence, including delay set.
		nvidia,dsi-suspend-stop-stream-late: keep DC stream enabled while issuing suspend sequence; DC stream
		will be stopped at the end of the suspend sequence.
		nvidia,dsi-late-resume-cmd: panel required late resume command sequence.
		nvidia,dsi-n-late-resume-cmd: command counts of late resume command sequence, including delay set.
		nvidia,dsi-pkt-seq: custom packet sequence since some panels need non standard packet sequence.
		nvidia,dsi-te-gpio: specifies a GPIO used for dsi panel TE signal.

		*/
		dsi {
			nvidia,dsi-controller-vs = <DSI_VS_1>;
			status = "okay";
			nvidia,active-panel = <&panel_a_wxga_8_0>;
			nvidia,dsi-csi-loopback;
		        compatible = "a,wxga-8-0";	
			nvidia,enable-hs-clk-in-lp-mode = <0x1>;
			panel-a-wxga-8-0 { //gst-launch-1.0 videotestsrc ! autovideosink
				status = "okay";
				/* Only 2 lanes used on Porg */
				nvidia,dsi-n-data-lanes = <2>;
				nvidia,panel-rst-gpio = <&gpio TEGRA_GPIO(S, 0) 0x0>;
				nvidia,panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(V, 0) 0x1>; // PV0
				nvidia,panel-bl-en-gpio = <&gpio TEGRA_GPIO(V, 1) 0x1>;
				
				/* Long  Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
				/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
				/* For DSI packets each DT cell is interpreted as u8 not u32 */
										
				//From Densitron
				nvidia,dsi-init-cmd = 
				 <TEGRA_DSI_DELAY_US 0x5>,
				/*<TEGRA_DSI_GPIO_SET 1>,
				// <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_NO_OP 0x00 0x00>,
				<TEGRA_DSI_DELAY_MS 1>,
				<TEGRA_DSI_GPIO_SET 0>,
				// <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_NO_OP 0x00 0x00>,
				<TEGRA_DSI_DELAY_MS 10>,
				<TEGRA_DSI_GPIO_SET 1>,
				// <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_NO_OP 0x00 0x00>,
				<TEGRA_DSI_DELAY_MS 200>,*/
				<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x06 0x00 0x00  0xFF 0xff 0x98 0x06 0x04 0x01 0x00 0x00>, // Change to Page 1 CMD 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x08 0x00 0x00>, //Output    SDA  
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x20 0x00 0x00>,//set DE/VSYNC mode //01 VSYNC MODE
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x21 0x01 0x00>,//DE = 1 Active  //01 
				//write_command(0x22);write_data(0x01);
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x30 0x02 0x00>, //Resolution setting 480 X 800  //02
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x31 0x00 0x00>, //Inversion setting //02-2dot
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x40 0x00 0x00>,  //BT DDVDH DDVDL  //10,14,18 00	2XVCI
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x41 0x44 0x00>,  //avdd +5.2v,avee-5.2v 33
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x42 0x00 0x00>, //VGL=DDVDH+VCIP -DDVDL,VGH=2DDVDL-VCIP  
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x43 0x80 0x00>, //SET VGH clamp level +15v
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x44 0x86 0x00>, //SET VGL clamp level -10v
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x46 0x34 0x00>,
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x50 0x94 0x00>, //VREG1 for positive Gamma  //A8
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x51 0x94 0x00>, //VREG2 for negative Gamma //A8
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x52 0x00 0x00>, //VCOM 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x53 0x67 0x00>, //VCOM  //Forward Flicker
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x54 0x00 0x00>, //VCOM 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x55 0x67 0x00>, //VCOM //Backward Flicker
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x60 0x07 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x61 0x04 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x08 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x63 0x04 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA0 0x00 0x00>, //Positive Gamma 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA1 0x0B 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA2 0x13 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA3 0x0C 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA4 0x05 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA5 0x0C 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA6 0x08 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA7 0x06 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA8 0x06 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xA9 0x0A 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xAA 0x0F 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xAB 0x06 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xAC 0x12 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xAD 0x18 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xAE 0x12 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xAF 0x0B 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC0 0x00 0x00>, //Negative Gamma 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC1 0x0B 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC2 0x13 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC3 0x0C 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC4 0x05 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC5 0x0C 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC6 0x08 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC7 0x06 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC8 0x06 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC9 0x0A 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xCA 0x0F 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xCB 0x06 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xCC 0x12 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xCD 0x18 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xCE 0x12 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xCF 0x0B 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x06 0x00 0x00 0xFF 0xFF 0x98 0x06 0x04 0x06 0x00 0x00>, // Change to Page 6 CMD for GIP timing   
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x00 0x21 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x01 0x0A 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x02 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x03 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x04 0x32 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x05 0x32 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x06 0x98 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x07 0x06 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x08 0x05 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x09 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0A 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0B 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0C 0x32 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0D 0x32 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0E 0x01 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0F 0x01 0x00>,
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x10 0xF0 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0xF0 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x12 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x13 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x14 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x15 0x43 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x16 0x0B 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x17 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x18 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x19 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1A 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1B 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1C 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1D 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x20 0x01 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x21 0x23 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x22 0x45 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x23 0x67 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x24 0x01 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x25 0x23 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x26 0x45 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x27 0x67 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x30 0x01 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x31 0x11 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x32 0x00 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x33 0x22 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x34 0x22 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0xcb 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0xda 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x37 0xAD 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x38 0xbc 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x39 0x66 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x77 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3B 0x22 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3C 0x22 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3D 0x22 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3E 0x22 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3F 0x22 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x40 0x22 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x52 0x10 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x06 0x00 0x00 0xFF 0xFF 0x98 0x06 0x04 0x07 0x00 0x00>, // Change to Page 7 CMD for GIP timing   
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x18 0x1d 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x02 0x77 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE1 0x79 0x00>, 
				<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x06 0x00 0x00 0xFF 0xFF 0x98 0x06 0x04 0x00 0x00 0x00>,// Change to Page 0 CMD for Normal command
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x01 0x00>,
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x70 0x00>, //24BIT
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x00 0x00>,
				<TEGRA_DSI_DELAY_MS 120>,
				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x00 0x00>,
				<TEGRA_DSI_DELAY_MS 25>;
				// <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x13 0x00 0x00>; // Hat keine Änderung gebracht
				nvidia,dsi-n-init-cmd = < 122 >;
				
				disp-default-out {
					nvidia,out-type = <TEGRA_DC_OUT_DSI>;
					nvidia,out-width = <107>;
					nvidia,out-height = <172>;
					nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE >;//Display has no fb
					nvidia,out-parent-clk = "pll_d_out0"; //"" ==>
					nvidia,out-xres = <480>;
					nvidia,out-yres = <800>;
				};
				display-timings {
					/delete-node/ 1200x1920-32;
					/delete-node/ 800x1280-32;
					
					480x800-32 {
						clock-frequency = <29448000>; //535*830*60		//608*835*60 	//horizontal total * vertical total * framerate 
						hactive = <480>; 
						vactive = <800>; 
[tegra210-p3448-0002-p3449-0000-b00.dts|attachment](upload://hbXYXczZaoK3rYrBGrU8Emehbjz.dts) (18.5 KB)
 range violated
						hsync-len = <10>; 
						vfront-porch = <16>; //dsi.vertical_frontporch=10 ==>Tlpx mipi range violated / mipi range violated
						vback-porch = <16>; // dsi.vertical_backporch=20 ==>Tlpx mipi range violated / mipi range violated
						vsync-len = <4>; 
						nvidia,h-ref-to-sync = <0>;
						nvidia,v-ref-to-sync = <0>;
					};
				};
				
				smartdimmer {
					status = "okay";
					nvidia,turn-off-brightness = <50>;
					nvidia,turn-on-brightness = <75>;
					nvidia,use-auto-pwm = <0>;
					nvidia,hw-update-delay = <0>;
					nvidia,bin-width = <0xffffffff>;
					nvidia,aggressiveness = <5>;
					nvidia,use-vid-luma = <0>;
					nvidia,phase-in-settings = <0>;
					nvidia,phase-in-adjustments = <0>;
					nvidia,k-limit-enable = <1>;
					nvidia,k-limit = <200>;
					nvidia,sd-window-enable = <0>;
					nvidia,soft-clipping-enable= <1>;
					nvidia,soft-clipping-threshold = <128>;
					nvidia,smooth-k-enable = <1>;
					nvidia,smooth-k-incr = <4>;
					nvidia,coeff = <5 9 2>;
					nvidia,fc = <0 0>;
					nvidia,blp = <1024 255>;
					nvidia,bltf = <57 65 73 82
						       92 103 114 125
						       138 150 164 178
						       193 208 224 241>;
					nvidia,lut = <255 255 255
						      199 199 199
						      153 153 153
						      116 116 116
						      85 85 85
						      59 59 59
						      36 36 36
						      17 17 17
						      0 0 0>;
					nvidia,use-vpulse2 = <1>;
					nvidia,bl-device-name = "pwm-backlight";
				};
			};
		};
	};

	backlight {
		compatible = "pwm-backlight";
		status = "okay";
		panel-a-wxga-8-0-bl {
			status = "okay";
			pwms = <&tegra_pwm 0 40161>;
			default-charge-brightness = <112>;
		};
	};

	chosen {
		/delete-property/  nvidia,bootloader-xusb-enable;
		nvidia,bootloader-xusb-disable;
	};
	rtc {
		status = "disabled";
	};
	pcie@1003000 {
		pci@2,0 {
			status = "disabled";
		};
	};
	pwm-fan {
		status = "disabled";
	};
[0003.134] hdmi is not connected
[0003.139] Panel: a,wxga-8-0 
[0003.141] Unsupported panel 
[0003.144] display_console_init: no valid display out_type

Does anybody know what exactly does it mean that panel is not supported?
Someone from Nvidia could help?
does it mean that Cboot does not support the display or that something is wrong with the provided configuration?

Yes, it means cboot does not support DSI panel.

Thank you @WayneWWW .
So to get it right, Cboot does not support DSI panels in general, or just the one that my hardware uses?
The kernel picks up the display without problems.
would there be an alternative solution in order to not have a black screen until the kernel boots?

Yes, cboot does not support DSI panel in general.

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