MIPI long packet // Jetson Xavier Nx

Robotics & Edge Computing Jetson Systems Jetson Xavier NX
1

Hello,

We are using Jetson Xavier NX for our one of project and sometime we see MIPI CSI2 error.

Question 1.

Is there a way to get the entire long packet along with headers in the buffer to analyze the error?

Detailed Breakdown of the 32-bit Packet Header (PH) we are looking at;

  • Data Identifier (DI) - 8 bits:

    • Virtual Channel (VC) - 2 bits: Identifies which of the four possible data streams (0–3) the packet belongs to.

    • Data Type (DT) - 6 bits: Defines the format of the payload data (e.g.,

  • Word Count (WC) - 16 bits: Specifies the number of 8-bit data words in the payload (0 to 65,535).

  • Error Correction Code (ECC) - 8 bits: Enables 1-bit error correction and 2-bit error detection for the DI and WC fields.

Long Packet Structure Context:

  • Header: 32-bit (DI + WC + ECC).

  • Payload: Variable number of 8-bit data words (defined by WC).

  • Footer: 16-bit Checksum (CRC).

Question 2.

Is possible to get two set of data with different Datatypes(DT) on the same virtual channel(VC)?

For example: below combination:

  1. Image data on VC0 and DT 0x2C
  2. Embedded data on VC0 and DT 0x12
3

Could any one clarify above questions?

4

Yes.

Analysis NVCSI register reporting

Please access Jetson Download Center for [Technical Reference Manual], you may see [NVCSI Registers] session for NVCSI register descriptions.
for example,

NVCSI_STREAM_0_PH_WC_0 / Status register on WC
Bit    Reset   Description
31:16  0x0     calc_wc: 16 bit WC computed over current packet (has to match with the WC in PH for a good packet)
 15:0  0x0     rx_wc: 16 bit WC from PH


NVCSI_STREAM_0_PF_CRC_0 / Status register on packet data CRC
Bit    Reset   Description
31:16  0x0     calc_crc: 16 bit CRC computed over current packet (has to match with the CRC in PF for a good packet)
 15:0  0x0     rx_crc: 16 bit CRC from PF

Check below link for more information.

5

Thank you for your reply.

I am using these registers and I can be read only at EOF.

Is any possibilities of reading these registers at ever line (line valid/vertical blanking) of MIPI received?

6

Not possible.

7

This means the registes NVCSI_STREAM_1_PH_WC_0, NVCSI_STREAM_1_PH_DI_0 etc I can read on per frame results.

8

Is this possible ?

9

Yes, can handle the embedded data with image data in the same channel.

10

Is this possible ?

With same DT(Data type) or can have different DT for image and embedded data in same VC?

11

Can have embedded data(0x12) and any others image data type combination.

12

Hi,

Yes, it’s totally possible to capture RAW12 (0x2C) + Embedded data (0x12), but make sure you defined the number of embedded data lines in your device-tree using the embedded_metadata_height property:

In my experience, I haven’t been able to capture 2 different data-types using the same VC if one of this two does not use the embedded metadata data-type (0x12). You should be good with DT=0x12.

Enrique Ramirez
Embedded SW Engineer at RidgeRun
Contact us: support@ridgerun.com
Developers wiki: https://developer.ridgerun.com
Website: www.ridgerun.com

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