PCIe lanes on the pinout

In the file named “NVIDIA Jetson Xavier NX and Jetson Nano Interface Comparison and Migration” in the download center the pinout of the PCIE has pins with duplicate numbers on the Xavier NX

134 PCIE0_TX0_N and later PCIE1_TX0_N should be 172
136 PCIE0_TX0_P and later PCIE1_TX0_P should be 174

133 PCIE0_RX0_N and later PCIE1_RX0_N should be 167
137 PCIE0_RX0_P and later PCIE1_RX0_P should be 169

160 PCIE0_CLK_N and later PCIE1_CLK_N should be 173
162 PCIE0_CLK_P and later PCIE1_CLK_P should be 175

180 PCIE1_CLKREQ* and later PCIE0_CLKREQ*
181 PCIE1_RST* and later PCIE0_RST*

It’s possible that someone copied the pins changed the names and forgot to change the pin numbers. Can someone please clarify this for me ? Also is the A02 pinout the same as B01 ?

Hi mic1hov,
Thanks, these were fixed and the updated doc will be released later.

For nano the B01 pinout is different to A02, customer should only follow B01 guide.