Hi, In our application, we are using PCIE0 port on M.2 Key M connector (J11) of NVIDIA Jetson NX board as Root Complex port, We need to confirm the what is Logic level IO standard used for the PCIE0 port, i.e., CML, LVPECL, LVDS etc. We have gone through the design guide and all other design rel…

No doc for HCSL info currently, it is from internal checking. The 50ohm termination is listed in the table of PCIe Interface Signal Routing Requirements in design guide.

PCIE Logic Level IO Standard for PCIE0 on M.2 Key M connector of Jetson NX

Robotics & Edge Computing Jetson & Embedded Systems Jetson Xavier NX

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PCIE Logic Level IO Standard for PCIE0 on M.2 Key M connector of Jetson NX

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