Pinmux excelsheet is not generating properly for GPIOs for JAXI

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
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1

We found that the pinmux xlsx sheet for Jetson AGX Xavier Industrial is not generating the proper ???-gpio-default.dtsi file for few GPIO pins.

GPIO entries for the following are not added to the ???-gpio-default.dtsi file when these pins are configured as GPIO in the excel sheet.
Hence in the generated .cfg file, these pins are still configured as SFIO instead of GPIO (10th bit is set)

  1. SOC_GPIO03 (PG.03)
  2. SOC_GPIO40 (PQ.04)
  3. SOC_GPIO53 (PN.00)
  4. SOC_GPIO54 (PN.01)

There could be more, but we found these

We don’t know why the excel sheet is creating issues for the above pins

3

Hi b-sathishkumar,

How did you generate pinmux for AGX Xavier Industrial?
Could you help to provide the detailed steps?

I’ve just checked SOC_GPIO03 (PG.03) in pinmux as following

image
image3245×40 3.88 KB

After generating the device tree, I could find the following.

In tegra19x-jetson_agx_industrial-gpio-default.dtsi

	gpio@2200000 {
		gpio-init-names = "default";
		gpio-init-0 = <&gpio_default>;

		gpio_default: default {
			gpio-input = <
				TEGRA_GPIO(S, 5)
				TEGRA_GPIO(S, 7)
				TEGRA_GPIO(T, 0)
				TEGRA_GPIO(T, 3)
				TEGRA_GPIO(G, 0)
				TEGRA_GPIO(G, 1)
				TEGRA_GPIO(G, 2)
				TEGRA_GPIO(G, 3)
               ..

In tegra19x-jetson_agx_industrial-pinmux.dtsi

			soc_gpio03_pg3 {
				nvidia,pins = "soc_gpio03_pg3";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

It seems been configured correctly as GPIO input pull-high.

Could you help to share yours?

4

Hi KevinFFF,

We tried in L4T 35.2.1
Did you try in 35.2.1 ?

Regards,
B.Sathish Kumar

5

Please use latest R35.3.1 to verify.

and It may not relate to Jetpack version.
The device tree files are directly generated from pinmux spreadsheet.
I’m using v1.06 pinmux spreadsheet for Jetson AGX Xavier Industrial as following.

Screenshot 2023-07-04 094009
Screenshot 2023-07-04 0940092485×480 158 KB

6

Sorry for the confusion

I am using 1.4 version of Jetson AGX Xavier Series Pinmux sheet

image
image955×220 36.6 KB

7

Sorry, I paste the wrong screenshot, which is for Xavier NX.
I used the same pinmux spreadsheet as yours for AGX Xavier.

Could you help to provide the generated .dtsi files for further check?

8

Sorry, it is for the following pin we found the issue

SOC_GPIO40 (PQ.04)

9

The following is the default configuration in pinmux spreadsheet for PQ.04.
It seems be configured as GPIO output w/o Drive (Z).

image
image3732×42 4.75 KB

You could see it in tegra19x-jetson_agx_industrial-pinmux.dtsi

			soc_gpio40_pq4 {
				nvidia,pins = "soc_gpio40_pq4";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

but not in tegra19x-jetson_agx_industrial-gpio-default.dtsi due to no Drive 0 or 1.

10

Since the PQ4 is not present in tegra19x-jetson_agx_industrial-gpio-default.dtsi (i.e., not in gpio-input, gpio-output-low and gpio-output-high), this pin is not added to gpio_list array by process_gpio_file function in pinmux-dts2cfg.py .

Hence the process_pinmux_file function in pinmux-dts2cfg.py generates the pinmux value for this as SFIO pin with 10th bit set (i.e., not a GPIO)

image
image1148×20 7.12 KB

11

If you configure it as Drive 0 or Drive 1, it will show in this dtsi.

12

Due to this issue, the sheet says PQ4 is configured as GPIO but in the SoC, the pinmux system wrongly configures PQ4 as SFIO because of the wrong entry in the CFG file which goes to the BCT partition. This is a problem, right ?

People will assume that PQ4 is configured as GPIO by the excel sheet while it is not actually configured as a GPIO but as a SFIO (Special Function IO)

13

Please let me check with internal and will update to you once there’s any result.

16

Hi b-sathishkumar,

Sorry for the late reply, I’ve checked this issue with internal.
The configuration for GPIO/Output/Z in an invalid combination.
We will update them in the document later.

17

Ok, Good to hear that !

19

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