Is this a mistake in the reference design? {Jetson AGX Orin Developer Kit Carrier Board Design Files (A05),Version: A05 - 20250205, Release Date: 2025/02/12}
Is this corrected in the latest production boards?
If the latest Revision Jetson AGX Orin Developer Kit follows same power sequence as shown in the above waveform?
Lastly, can please give your suggestions/recommendations.
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Based on the provided context, I’ll address the questions and provide a comprehensive answer.
Question 1: Is this a mistake in the reference design?
The provided waveform shows a deviation from the recommended power sequencing between SYSVINMV and SYSVINHV in the design guide. However, it’s mentioned that the same Button MCU and pass FET circuits as in the reference design are used. This suggests that the reference design itself might have a different power sequencing than what’s recommended in the design guide.
Question 2: Is this corrected in the latest production boards?
The latest production boards might follow the same power sequence as shown in the waveform, but this is not explicitly confirmed. It’s possible that the latest production boards still have the same deviation as the reference design.
Question 3: Does the latest Revision follow the same power sequence as shown in the above waveform?
Unfortunately, the provided context does not explicitly confirm whether the latest Revision follows the same power sequence as shown in the waveform. However, it’s likely that the latest Revision might still have the same deviation as the reference design.
Recommendations and Suggestions:
Verify the power sequencing: Double-check the power sequencing between SYSVINMV and SYSVINHV in the custom carrier board design to ensure it aligns with the recommended sequence in the design guide.
Consult the latest design guide: Ensure that the custom carrier board design is based on the latest design guide (DG-10931-001_v1.4) and not an older version.
Compare with the reference design: Compare the custom carrier board design with the reference design (P3768 carrier board) to identify any differences in the power sequencing.
Contact NVIDIA support: Reach out to NVIDIA support for further clarification and guidance on the power sequencing deviation.
Consider updating the design: If the deviation is confirmed to be a mistake, consider updating the custom carrier board design to align with the recommended power sequencing in the design guide.
In summary, while the provided context suggests that the reference design might have a different power sequencing than what’s recommended in the design guide, it’s essential to verify the power sequencing in the custom carrier board design and consult the latest design guide to ensure compliance.
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The reference design followed the power on sequencing shown in previous releases of the Design Guide where HV preceded MV, but v1.8 of the Design Guide is revised to show the MV rail should be fully powered on ≥1ms before HV turns on. So it is not exactly a mistake in the reference design, but an update to the requirement after the reference design released.
Please follow the MV before HV sequence shown in v1.8 of the Design Guide.
The AGX Orin Dev Kit is not updated for this change, but any custom carrier board designs should follow the MV before HV sequencing in the v1.8 Design Guide.
Since the sequencing is done on the carrier board side, there is no change to make on the Jetson AGX Orin modules in production.
Hi Chris,
•Which version of the design guide is the reference design based on?
We have the Jetson AGX Orin Developer Kit 180-13737-DAAF-A15 (Model: P3737 699-13737-0000-500 K). The latest reference concept design files are Jetson AGX Orin Developer Kit Carrier Board Design Files (A05),Version: A05 - 20250205, Release Date: 2025/02/12 and the latest design guide at the time for this is Jetson AGX Orin Series Design Guide (including AGX Orin Industrial) V1.7,Release Date: 2024/11/15 or the previous version V1.6 both specifies the SYS_VIN_MV before SYS_VIN_HV ≥ 1ms condition.
•What are the effects of this deviated power sequence on the SOM? And What was the reason for this correction for the design?
The following deviations were also found in the power down sequence in the Jetson AGX Orin Developer Kit:
1. Carrier board I/O voltages turn off in ≤ 1.4ms is not followed.
• Can you confirm if the condition SYS_VIN_MV below 100mV before next power up followed in the Jetson AGX Orin Developer Kit? And what are the effects on the SOM if this is not followed?
If my reasoning is correct, the delay in the SYS_VIN_SV / 3V3_AO and SYS_VIN_MV / VDD_5V0 is introduced by the PD-Controller in the ACOK signal to the button MCU for the SYS_VIN_MV to come below 100mV. I was only able to get these waveforms from the devkit without dismantling it. From these waveforms alone I can’t confirm if the condition SYS_VIN_MV < 100mV is met on the Dev Kit as the time from PD controller supply turn on to VIN_PWR_ON high has to be considered. By a rough estimate from the waveforms and Dev Kit turn on time, I think the SYS_VIN_MV < 100mV for subsequent power on will not be met on the Dev Kit (I may be wrong). Can you please confirm the same?
• Is the reference design {Jetson AGX Orin Developer Kit Carrier Board Design Files (A05),Version: A05 - 20250205, Release Date: 2025/02/12} compatible with JAOi (Jetson AGX Orin Industrial) SOM?
• There is no timing requirement specified for the power-down sequence. While the order is defined, is it required that each rail fully powers down before the subsequent rail begins to power down?
