Question about DDR3L schematic (JETSON TK1)

Hi All,
I was wondering why the the balls L1, J1, J9 (Not connected) of the Hynix DDR3L are wired to the DDR3 controller ?
Thanks in advance.

To make it work with dual rank chips (e.g. Micron MT41K512M16) as DDR3L footrints and wiring on Jetson TK1 are universal