DDR connection problem

I have viewed the jetson schematic and trying to compare with my custom board.
I have a confusion about DDR CS pins.
According to Design Guide
page # 29
Tegra Ball # : Tegra Ball Name : DDR3L Net Name : DDR Device : DDR Ball # : DDR Ball Name

B14 : DDR_CS0_N : DDR0_CS1_L : 1 & 2 : L1 : CS1_L

Now when i see the datasheet of DDR, the ball L1 is NC. this should be not connected.
So, can you explain the purpose of these CS pins.

Hi, is your DDR in the TK1 supported component list? https://developer.nvidia.com/embedded/dlc/tegra-k1-supported-component-list

we are using this part number for DDR MT41K256M16TW-107 AUT:P
and for Tegra it is CD575M-A1
I think this is in the supported list of components.

So, it is pin compatible to reference design, you can keep that connection same as dev kit. It is a backup design for two CS DDR.

Also you can check the TK1_MemoryCharacterization_AppNote in shmoo package for the note: if your design does not use CS1/CKE1/ODT1 and the pins are NC, CS0/CKE0/ODT0 are the values of CS1/CKE1/ODT1, respectively.

We tried to follow reference schematic but for the CS pins, we connected these in the same way for chip 1 & 2 but for DDR chip 3 & 4, we mistakenly swapped the pins.
DDR1_CS0_L (A19) of processor should be connected to CS0_L(L2) of DDR chips 3 & 4
DDR1_CS1_L (A18) of processor should be connected to CS1_L(L1) of DDR chips 3 & 4

but in our case, these are
DDR1_CS0_L (A19) of processor is connected to CS1_L(L1) of DDR chips 3 & 4
DDR1_CS1_L (A18) of processor is connected to CS0_L(L2) of DDR chips 3 & 4

What can be its affect on RAM working.
Should we need anything in any configuration file or we must have to rework on hardware. We need your suggestion in this problem.

Basically that should be corrected, otherwise DDR might not work.

we just saw the swizzling files in shmoo folder, we found the file for data swizzling only, can we find the file where control signals are swizzled?
as we can see from schematics that DDR1_CS1_L is connected on processor DDR_ODT_B1 (A18), so i think there should be a file where control signals can be swizzled should be defined.

No such file for CS pin. DDR1_CS1_L is connected to A18 in pin multiplexing option #14. There are only two options available as you can see in guide, option #10 and option #14.

Thanks for your instant replies. Can we use only 1GiB with tegra. as it seems difficult to do rework in chip 3 & 4 ?

I’m afraid not in this situation.