Question about PCIe output reference clock for Controller Number mapping

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

Question about PCIe controller # mapping.
In Jetson_AGX_Orin_Series_Design_Guide_DG-10653-001_v1.2.pdf, “PCIe output Reference clock for controller #xxx” is described.

How can I match PCIe vs PCIe controller #xxx?
Where can I refer to the document that described this?

2

Design guide already has the mapping in the PCIe section. Could you check it again?

If you still not able to find it, please share a screenshot for what you are read.

3

Dear WayneWWW,

Below “Table 7-12.” of Design Guide page 43, in “Usage/Description” example listed as “PCI output Reference Clock for controller”, how can I match Controller #0 to #10 of PCIe (UPHY_TXxx_P/N)?

For example, If I want to use four (4) PCIe then also what PCIe Reference clock should I select and use for these PCIe signals?

Orin DG Table 7-12
Orin DG Table 7-121051×841 138 KB

Regards,

5

You can get the mapping in Table 7-4. USB 3.2, PCIe, and MGBE Mapping Options.

6

Thank you for your description.
Other questions are as follows.

  1. Q1
    ---- As your mentioned Table 7-4 listed (C0), (C1), C4), (C5), and (C7). Does it mean Controller #0, 1, 4, 5, 7 of blocks 0, 1, 2?
  2. Q2
    ---- In the case of MGBE (C0) for UPHY_RX6/TX6 is used for 10G with the “Configuration #1”, and other UPHY2 Lane0~3, and Lane 5~7 can be used PCIe x8 “Configuration #2” mode is possible?

Than

7

Q1-> Yes. That means the controller #.

Q2-> No, when you enable MGBE, the other UPHY2 lane cannot be working as PCIe.

image
image675×672 45.9 KB

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8

GOOOOOOOOOOOOOOD!!!
Thank you very much.

---- Can I have another controller # not mentioned in Table 7-2 mapping with PCIe or other matching signals that are listed in Table 7-12 and Table 7-13.? (C6, C8, C10)
---- Because I will use several PCIe in the new design Carrier Board.

9

No, only these PCIe are available on Orin AGX.

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10

---- I want to design four(4) PCIe lanes instead of implementing a PCIe connector that assigned Lane 0 ~ 7 of UPHY1. (for 4 PCI to 4 Giga Ethernet)

---- Q1
The Dev. Kit has a PICe connector involving x16 by using only one reference clock (PCIE5_CLK_P/N), but if I use another four(4) PCIe interface chips (PCIe to Ethernet controller) instead of the PCIe connector by using PCIe lanes of this connector connected, should I add Reference clock distributor buffer chip (ex: PI6CB33602) for the PLL FAN buffer out to four each four PCIe to Ethernet controller chips?

Regards,

13

Hi, only the lane mapping in Design Guide can be supported. Please read the guide and make custom design.

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15

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