---- Can I have another controller # not mentioned in Table 7-2 mapping with PCIe or other matching signals that are listed in Table 7-12 and Table 7-13.? (C6, C8, C10)
---- Because I will use several PCIe in the new design Carrier Board.
---- I want to design four(4) PCIe lanes instead of implementing a PCIe connector that assigned Lane 0 ~ 7 of UPHY1. (for 4 PCI to 4 Giga Ethernet)
The Dev. Kit has a PICe connector involving x16 by using only one reference clock (PCIE5_CLK_P/N), but if I use another four(4) PCIe interface chips (PCIe to Ethernet controller) instead of the PCIe connector by using PCIe lanes of this connector connected, should I add Reference clock distributor buffer chip (ex: PI6CB33602) for the PLL FAN buffer out to four each four PCIe to Ethernet controller chips?