SPI disabling i2c and vice-versa on Developer Kit

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
22

Hi,

This is the output of sudo cat /sys/kernel/debug/tegra_pinctrl_reg:

Bank: 1 Reg: 0x0c302000 Val: 0x00000056 → touch_clk_pcc4
Bank: 1 Reg: 0x0c302008 Val: 0x00000450 → uart3_rx_pcc6
Bank: 1 Reg: 0x0c302010 Val: 0x00000400 → uart3_tx_pcc5
Bank: 1 Reg: 0x0c302018 Val: 0x00000560 → gen8_i2c_sda_pdd2
Bank: 1 Reg: 0x0c302020 Val: 0x00000560 → gen8_i2c_scl_pdd1
Bank: 1 Reg: 0x0c302028 Val: 0x00000002 → spi2_mosi_pcc2
Bank: 1 Reg: 0x0c302030 Val: 0x00000460 → gen2_i2c_scl_pcc7
Bank: 1 Reg: 0x0c302038 Val: 0x00000002 → spi2_cs0_pcc3
Bank: 1 Reg: 0x0c302040 Val: 0x00000460 → gen2_i2c_sda_pdd0
Bank: 1 Reg: 0x0c302048 Val: 0x00000002 → spi2_sck_pcc0
Bank: 1 Reg: 0x0c302050 Val: 0x00000002 → spi2_miso_pcc1
Bank: 1 Reg: 0x0c303000 Val: 0x0000c415 → can1_dout_paa0
Bank: 1 Reg: 0x0c303008 Val: 0x0000c415 → can1_din_paa1
Bank: 1 Reg: 0x0c303010 Val: 0x0000c400 → can0_dout_paa2
Bank: 1 Reg: 0x0c303018 Val: 0x0000c450 → can0_din_paa3
Bank: 1 Reg: 0x0c303020 Val: 0x0000c414 → can0_stb_paa4
Bank: 1 Reg: 0x0c303028 Val: 0x0000c000 → can0_en_paa5
Bank: 1 Reg: 0x0c303030 Val: 0x0000c414 → can0_wake_paa6
Bank: 1 Reg: 0x0c303038 Val: 0x0000c414 → can0_err_paa7
Bank: 1 Reg: 0x0c303040 Val: 0x0000c414 → can1_stb_pbb0
Bank: 1 Reg: 0x0c303048 Val: 0x0000c414 → can1_en_pbb1
Bank: 1 Reg: 0x0c303050 Val: 0x0000c414 → can1_wake_pbb2
Bank: 1 Reg: 0x0c303058 Val: 0x0000c414 → can1_err_pbb3
Bank: 0 Reg: 0x02431000 Val: 0x00000414 → soc_gpio33_pt0
Bank: 0 Reg: 0x02431008 Val: 0x00000058 → soc_gpio32_ps7
Bank: 0 Reg: 0x02431010 Val: 0x00000414 → soc_gpio31_ps6
Bank: 0 Reg: 0x02431018 Val: 0x00000414 → soc_gpio30_ps5
Bank: 0 Reg: 0x02431020 Val: 0x00000059 → aud_mclk_ps4
Bank: 0 Reg: 0x02431028 Val: 0x00000415 → dap1_fs_ps3
Bank: 0 Reg: 0x02431030 Val: 0x00000415 → dap1_din_ps2
Bank: 0 Reg: 0x02431038 Val: 0x00000415 → dap1_dout_ps1
Bank: 0 Reg: 0x02431040 Val: 0x00000415 → dap1_sclk_ps0
Bank: 0 Reg: 0x02431048 Val: 0x00000440 → dap3_fs_pt4
Bank: 0 Reg: 0x02431050 Val: 0x00000450 → dap3_din_pt3
Bank: 0 Reg: 0x02431058 Val: 0x00000400 → dap3_dout_pt2
Bank: 0 Reg: 0x02431060 Val: 0x00000440 → dap3_sclk_pt1
Bank: 0 Reg: 0x02431068 Val: 0x00000057 → dap5_fs_pu0
Bank: 0 Reg: 0x02431070 Val: 0x00000057 → dap5_din_pt7
Bank: 0 Reg: 0x02431078 Val: 0x00000056 → dap5_dout_pt6
Bank: 0 Reg: 0x02431080 Val: 0x00000056 → dap5_sclk_pt5
Bank: 0 Reg: 0x02432000 Val: 0x0000c416 → dap6_fs_pa3
Bank: 0 Reg: 0x02432008 Val: 0x0000c416 → dap6_din_pa2
Bank: 0 Reg: 0x02432010 Val: 0x0000c416 → dap6_dout_pa1
Bank: 0 Reg: 0x02432018 Val: 0x0000c416 → dap6_sclk_pa0
Bank: 0 Reg: 0x02432020 Val: 0x0000c416 → dap4_fs_pa7
Bank: 0 Reg: 0x02432028 Val: 0x0000c416 → dap4_din_pa6
Bank: 0 Reg: 0x02432030 Val: 0x0000c416 → dap4_dout_pa5
Bank: 0 Reg: 0x02432038 Val: 0x0000c416 → dap4_sclk_pa4
Bank: 0 Reg: 0x02430000 Val: 0x00000400 → extperiph2_clk_pp1
Bank: 0 Reg: 0x02430008 Val: 0x00000400 → extperiph1_clk_pp0
Bank: 0 Reg: 0x02430010 Val: 0x00000460 → cam_i2c_sda_pp3
Bank: 0 Reg: 0x02430018 Val: 0x00000460 → cam_i2c_scl_pp2
Bank: 0 Reg: 0x02430020 Val: 0x00000426 → soc_gpio40_pq4
Bank: 0 Reg: 0x02430028 Val: 0x0000005a → soc_gpio41_pq5
Bank: 0 Reg: 0x02430030 Val: 0x0000005a → soc_gpio42_pq6
Bank: 0 Reg: 0x02430038 Val: 0x00000426 → soc_gpio43_pq7
Bank: 0 Reg: 0x02430040 Val: 0x00000056 → soc_gpio44_pr0
Bank: 0 Reg: 0x02430048 Val: 0x00000021 → soc_gpio45_pr1
Bank: 0 Reg: 0x02430050 Val: 0x00000414 → soc_gpio20_pq0
Bank: 0 Reg: 0x02430058 Val: 0x00000054 → soc_gpio21_pq1
Bank: 0 Reg: 0x02430060 Val: 0x00000459 → soc_gpio22_pq2
Bank: 0 Reg: 0x02430068 Val: 0x00000058 → soc_gpio23_pq3
Bank: 0 Reg: 0x02430070 Val: 0x00000000 → soc_gpio04_pp4
Bank: 0 Reg: 0x02430078 Val: 0x00000000 → soc_gpio05_pp5
Bank: 0 Reg: 0x02430080 Val: 0x00000414 → soc_gpio06_pp6
Bank: 0 Reg: 0x02430088 Val: 0x0000045a → soc_gpio07_pp7
Bank: 0 Reg: 0x02430090 Val: 0x00000055 → uart1_cts_pr5
Bank: 0 Reg: 0x02430098 Val: 0x00000055 → uart1_rts_pr4
Bank: 0 Reg: 0x024300a0 Val: 0x00000454 → uart1_rx_pr3
Bank: 0 Reg: 0x024300a8 Val: 0x00000400 → uart1_tx_pr2
Bank: 0 Reg: 0x02434000 Val: 0x00000415 → dap2_din_pi1
Bank: 0 Reg: 0x02434008 Val: 0x00000415 → dap2_dout_pi0
Bank: 0 Reg: 0x02434010 Val: 0x00000415 → dap2_fs_pi2
Bank: 0 Reg: 0x02434018 Val: 0x00000415 → dap2_sclk_ph7
Bank: 0 Reg: 0x02434020 Val: 0x00000415 → uart4_cts_ph6
Bank: 0 Reg: 0x02434028 Val: 0x00000051 → uart4_rts_ph5
Bank: 0 Reg: 0x02434030 Val: 0x00000415 → uart4_rx_ph4
Bank: 0 Reg: 0x02434038 Val: 0x00000051 → uart4_tx_ph3
Bank: 0 Reg: 0x02434040 Val: 0x00000004 → soc_gpio03_pg3
Bank: 0 Reg: 0x02434048 Val: 0x00000000 → soc_gpio02_pg2
Bank: 0 Reg: 0x02434050 Val: 0x00000414 → soc_gpio01_pg1
Bank: 0 Reg: 0x02434058 Val: 0x00000058 → soc_gpio00_pg0
Bank: 0 Reg: 0x02434060 Val: 0x00000540 → gen1_i2c_scl_pi3
Bank: 0 Reg: 0x02434068 Val: 0x00000540 → gen1_i2c_sda_pi4
Bank: 0 Reg: 0x02434070 Val: 0x00000050 → soc_gpio08_pg4
Bank: 0 Reg: 0x02434078 Val: 0x00000414 → soc_gpio09_pg5
Bank: 0 Reg: 0x02434080 Val: 0x00000400 → soc_gpio10_pg6
Bank: 0 Reg: 0x02434088 Val: 0x00000058 → soc_gpio11_pg7
Bank: 0 Reg: 0x02434090 Val: 0x00000414 → soc_gpio12_ph0
Bank: 0 Reg: 0x02434098 Val: 0x00000401 → soc_gpio13_ph1
Bank: 0 Reg: 0x024340a0 Val: 0x00000414 → soc_gpio14_ph2
Bank: 0 Reg: 0x02435008 Val: 0x00022414 → directdc1_out7_pw1
Bank: 0 Reg: 0x02435010 Val: 0x00022414 → directdc1_out6_pw0
Bank: 0 Reg: 0x02435018 Val: 0x00022414 → directdc1_out5_pv7
Bank: 0 Reg: 0x02435020 Val: 0x00022414 → directdc1_out4_pv6
Bank: 0 Reg: 0x02435028 Val: 0x00022414 → directdc1_out3_pv5
Bank: 0 Reg: 0x02435030 Val: 0x00022414 → directdc1_out2_pv4
Bank: 0 Reg: 0x02435038 Val: 0x00022414 → directdc1_out1_pv3
Bank: 0 Reg: 0x02435040 Val: 0x00022414 → directdc1_out0_pv2
Bank: 0 Reg: 0x02435048 Val: 0x00022454 → directdc1_in_pv1
Bank: 0 Reg: 0x02435050 Val: 0x00022414 → directdc1_clk_pv0
Bank: 0 Reg: 0x02435058 Val: 0x00002000 → directdc_comp
Bank: 0 Reg: 0x02440000 Val: 0x00000414 → soc_gpio50_pm5
Bank: 0 Reg: 0x02440008 Val: 0x00000414 → soc_gpio51_pm6
Bank: 0 Reg: 0x02440010 Val: 0x00000414 → soc_gpio52_pm7
Bank: 0 Reg: 0x02440018 Val: 0x00000004 → soc_gpio53_pn0
Bank: 0 Reg: 0x02440020 Val: 0x00000054 → soc_gpio54_pn1
Bank: 0 Reg: 0x02440028 Val: 0x00000414 → soc_gpio55_pn2
Bank: 0 Reg: 0x02440030 Val: 0x00000450 → dp_aux_ch0_hpd_pm0
Bank: 0 Reg: 0x02440038 Val: 0x00000150 → dp_aux_ch1_hpd_pm1
Bank: 0 Reg: 0x02440040 Val: 0x00000416 → dp_aux_ch2_hpd_pm2
Bank: 0 Reg: 0x02440048 Val: 0x00000416 → dp_aux_ch3_hpd_pm3
Bank: 0 Reg: 0x02440050 Val: 0x00000460 → hdmi_cec_pm4
Bank: 0 Reg: 0x02445000 Val: 0x00022400 → eqos_td3_pe4
Bank: 0 Reg: 0x02445008 Val: 0x00022400 → eqos_td2_pe3
Bank: 0 Reg: 0x02445010 Val: 0x00022400 → eqos_td1_pe2
Bank: 0 Reg: 0x02445018 Val: 0x00022400 → eqos_td0_pe1
Bank: 0 Reg: 0x02445020 Val: 0x00022440 → eqos_rd3_pf1
Bank: 0 Reg: 0x02445028 Val: 0x00022440 → eqos_rd2_pf0
Bank: 0 Reg: 0x02445030 Val: 0x00022440 → eqos_rd1_pe7
Bank: 0 Reg: 0x02445038 Val: 0x00022440 → eqos_sma_mdio_pf4
Bank: 0 Reg: 0x02445040 Val: 0x00022440 → eqos_rd0_pe6
Bank: 0 Reg: 0x02445048 Val: 0x00022400 → eqos_sma_mdc_pf5
Bank: 0 Reg: 0x02445050 Val: 0x00002000 → eqos_comp
Bank: 0 Reg: 0x02445058 Val: 0x00022400 → eqos_txc_pe0
Bank: 0 Reg: 0x02445060 Val: 0x00022440 → eqos_rxc_pf3
Bank: 0 Reg: 0x02445068 Val: 0x00022400 → eqos_tx_ctl_pe5
Bank: 0 Reg: 0x02445070 Val: 0x00022440 → eqos_rx_ctl_pf2
Bank: 0 Reg: 0x02437000 Val: 0x00000415 → pex_l2_clkreq_n_pk4
Bank: 0 Reg: 0x02437008 Val: 0x00000178 → pex_wake_n_pl2
Bank: 0 Reg: 0x02437010 Val: 0x00000415 → pex_l1_clkreq_n_pk2
Bank: 0 Reg: 0x02437018 Val: 0x00000415 → pex_l1_rst_n_pk3
Bank: 0 Reg: 0x02437020 Val: 0x00000415 → pex_l0_clkreq_n_pk0
Bank: 0 Reg: 0x02437028 Val: 0x00000415 → pex_l0_rst_n_pk1
Bank: 0 Reg: 0x02437030 Val: 0x00000415 → pex_l2_rst_n_pk5
Bank: 0 Reg: 0x02437038 Val: 0x00000415 → pex_l3_clkreq_n_pk6
Bank: 0 Reg: 0x02437040 Val: 0x00000415 → pex_l3_rst_n_pk7
Bank: 0 Reg: 0x02437048 Val: 0x00000560 → pex_l4_clkreq_n_pl0
Bank: 0 Reg: 0x02437050 Val: 0x00000520 → pex_l4_rst_n_pl1
Bank: 0 Reg: 0x02437058 Val: 0x00000415 → sata_dev_slp_pl3
Bank: 0 Reg: 0x02444000 Val: 0x00000560 → pex_l5_clkreq_n_pgg0
Bank: 0 Reg: 0x02444008 Val: 0x00000520 → pex_l5_rst_n_pgg1
Bank: 0 Reg: 0x02446000 Val: 0x00000414 → cpu_pwr_req_1_pb1
Bank: 0 Reg: 0x02446008 Val: 0x00000000 → cpu_pwr_req_0_pb0
Bank: 0 Reg: 0x0243b000 Val: 0x00023440 → qspi0_io3_pc5
Bank: 0 Reg: 0x0243b008 Val: 0x00023440 → qspi0_io2_pc4
Bank: 0 Reg: 0x0243b010 Val: 0x00023440 → qspi0_io1_pc3
Bank: 0 Reg: 0x0243b018 Val: 0x00023440 → qspi0_io0_pc2
Bank: 0 Reg: 0x0243b020 Val: 0x00023460 → qspi0_sck_pc0
Bank: 0 Reg: 0x0243b028 Val: 0x00023400 → qspi0_cs_n_pc1
Bank: 0 Reg: 0x0243b030 Val: 0x00023415 → qspi1_io3_pd3
Bank: 0 Reg: 0x0243b038 Val: 0x00023415 → qspi1_io2_pd2
Bank: 0 Reg: 0x0243b040 Val: 0x00023415 → qspi1_io1_pd1
Bank: 0 Reg: 0x0243b048 Val: 0x00023415 → qspi1_io0_pd0
Bank: 0 Reg: 0x0243b050 Val: 0x00023435 → qspi1_sck_pc6
Bank: 0 Reg: 0x0243b058 Val: 0x00023415 → qspi1_cs_n_pc7
Bank: 0 Reg: 0x0243b060 Val: 0x00002000 → qspi_comp
Bank: 0 Reg: 0x02438000 Val: 0x0000a460 → sdmmc1_clk_pj0
Bank: 0 Reg: 0x02438008 Val: 0x0000a448 → sdmmc1_cmd_pj1
Bank: 0 Reg: 0x02438010 Val: 0x00000000 → sdmmc1_comp
Bank: 0 Reg: 0x02438018 Val: 0x0000a448 → sdmmc1_dat3_pj5
Bank: 0 Reg: 0x02438020 Val: 0x0000a448 → sdmmc1_dat2_pj4
Bank: 0 Reg: 0x02438028 Val: 0x0000a448 → sdmmc1_dat1_pj3
Bank: 0 Reg: 0x02438030 Val: 0x0000a448 → sdmmc1_dat0_pj2
Bank: 0 Reg: 0x0243a000 Val: 0x0000a448 → sdmmc3_dat3_po5
Bank: 0 Reg: 0x0243a008 Val: 0x0000a448 → sdmmc3_dat2_po4
Bank: 0 Reg: 0x0243a010 Val: 0x0000a448 → sdmmc3_dat1_po3
Bank: 0 Reg: 0x0243a018 Val: 0x0000a448 → sdmmc3_dat0_po2
Bank: 0 Reg: 0x0243a020 Val: 0x00000000 → sdmmc3_comp
Bank: 0 Reg: 0x0243a028 Val: 0x0000a448 → sdmmc3_cmd_po1
Bank: 0 Reg: 0x0243a030 Val: 0x0000a460 → sdmmc3_clk_po0
Bank: 0 Reg: 0x02436008 Val: 0x00002060 → sdmmc4_clk
Bank: 0 Reg: 0x02436010 Val: 0x00002040 → sdmmc4_cmd
Bank: 0 Reg: 0x02436018 Val: 0x00000040 → sdmmc4_dqs
Bank: 0 Reg: 0x02436020 Val: 0x00002048 → sdmmc4_dat7
Bank: 0 Reg: 0x02436028 Val: 0x00002048 → sdmmc4_dat6
Bank: 0 Reg: 0x02436030 Val: 0x00002048 → sdmmc4_dat5
Bank: 0 Reg: 0x02436038 Val: 0x00002048 → sdmmc4_dat4
Bank: 0 Reg: 0x02436040 Val: 0x00002048 → sdmmc4_dat3
Bank: 0 Reg: 0x02436048 Val: 0x00002048 → sdmmc4_dat2
Bank: 0 Reg: 0x02436050 Val: 0x00002048 → sdmmc4_dat1
Bank: 0 Reg: 0x02436058 Val: 0x00002048 → sdmmc4_dat0
Bank: 1 Reg: 0x0c301000 Val: 0x00000000 → shutdown_n
Bank: 1 Reg: 0x0c301008 Val: 0x00000040 → pmu_int_n
Bank: 1 Reg: 0x0c301010 Val: 0x00000051 → safe_state_pee0
Bank: 1 Reg: 0x0c301018 Val: 0x00000458 → vcomp_alert_pee1
Bank: 1 Reg: 0x0c301020 Val: 0x00000000 → soc_pwr_req
Bank: 1 Reg: 0x0c301028 Val: 0x00000458 → batt_oc_pee3
Bank: 1 Reg: 0x0c301030 Val: 0x00001000 → clk_32k_in
Bank: 1 Reg: 0x0c301038 Val: 0x00000058 → power_on_pee4
Bank: 1 Reg: 0x0c301040 Val: 0x00000440 → pwr_i2c_scl_pee5
Bank: 1 Reg: 0x0c301048 Val: 0x00000440 → pwr_i2c_sda_pee6
Bank: 1 Reg: 0x0c301060 Val: 0x00000415 → ao_retention_n_pee2
Bank: 0 Reg: 0x0243d000 Val: 0x00000000 → gpu_pwr_req_px0
Bank: 0 Reg: 0x0243d008 Val: 0x00000055 → spi3_miso_py1
Bank: 0 Reg: 0x0243d010 Val: 0x00000448 → spi1_cs0_pz6
Bank: 0 Reg: 0x0243d018 Val: 0x00000055 → spi3_cs0_py3
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 → spi1_miso_pz4
Bank: 0 Reg: 0x0243d028 Val: 0x00000055 → spi3_cs1_py4
Bank: 0 Reg: 0x0243d030 Val: 0x00000415 → gp_pwm3_px3
Bank: 0 Reg: 0x0243d038 Val: 0x00000400 → gp_pwm2_px2
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 → spi1_sck_pz3
Bank: 0 Reg: 0x0243d048 Val: 0x00000055 → spi3_sck_py0
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 → spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 → spi1_mosi_pz5
Bank: 0 Reg: 0x0243d060 Val: 0x00000055 → spi3_mosi_py2
Bank: 0 Reg: 0x0243d068 Val: 0x00000414 → cv_pwr_req_px1
Bank: 0 Reg: 0x0243d070 Val: 0x00000400 → uart2_tx_px4
Bank: 0 Reg: 0x0243d078 Val: 0x00000450 → uart2_rx_px5
Bank: 0 Reg: 0x0243d080 Val: 0x00000408 → uart2_rts_px6
Bank: 0 Reg: 0x0243d088 Val: 0x00000458 → uart2_cts_px7
Bank: 0 Reg: 0x0243d090 Val: 0x00000415 → uart5_rx_py6
Bank: 0 Reg: 0x0243d098 Val: 0x00000051 → uart5_tx_py5
Bank: 0 Reg: 0x0243d0a0 Val: 0x00000051 → uart5_rts_py7
Bank: 0 Reg: 0x0243d0a8 Val: 0x00000415 → uart5_cts_pz0
Bank: 0 Reg: 0x0243d0b0 Val: 0x00000059 → usb_vbus_en0_pz1
Bank: 0 Reg: 0x0243d0b8 Val: 0x00000415 → usb_vbus_en1_pz2
Bank: 0 Reg: 0x02441000 Val: 0x00022415 → ufs0_rst_pff1
Bank: 0 Reg: 0x02441008 Val: 0x00022415 → ufs0_ref_clk_pff0

Checking with devmem2:
sudo devmem2 0x0243d040

/dev/mem opened.
Memory mapped at address 0x7f925b5000.
Value at address 0x243D040 (0x7f925b5040): 0x444

sudo devmem2 0x0243d010

/dev/mem opened.
Memory mapped at address 0x7f85501000.
Value at address 0x243D010 (0x7f85501010): 0x448

sudo devmem2 0x0243d020

/dev/mem opened.
Memory mapped at address 0x7f88a9e000.
Value at address 0x243D020 (0x7f88a9e020): 0x444

sudo devmem2 0x0243d050

/dev/mem opened.
Memory mapped at address 0x7f943bd000.
Value at address 0x243D050 (0x7f943bd050): 0x448

sudo devmem2 0x0243d058

/dev/mem opened.
Memory mapped at address 0x7fb2220000.
Value at address 0x243D058 (0x7fb2220058): 0x444

23

Those REG is correct. Could you check the loopback test to verify it.

24

I have connected pins 19 and 21 together and ran ./spidev_test -v and got the following output:

sudo ./spidev_test -v
can’t open device: No such file or directory
Aborted

I have checked in /dev/ and there is no spi device.
After running sudo modprobe spidev I get the following output for lsmod | grep -i spi:

spidev 13282 0

But ls -l /dev/spi* gives the following output:

ls: cannot access ‘/dev/spi*’: No such file or directory

25

You need below context for spidev driver.

	spi@3210000 {
		compatible = "nvidia,tegra186-spi";
		reg = <0x0 0x3210000 0x0 0x10000>;
		interrupts = <0x0 0x24 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		iommus = <0x2 0x20>;
		dma-coherent;
		dmas = <0x19 0xf 0x19 0xf>;
		dma-names = "rx", "tx";
		spi-max-frequency = <0x3dfd240>;
		nvidia,clk-parents = "pll_p", "clk_m";
		clocks = <0x4 0x87 0x4 0x66 0x4 0xe>;
		clock-names = "spi", "pll_p", "clk_m";
		resets = <0x5 0x5b>;
		reset-names = "spi";
		status = "okay";
		linux,phandle = <0xf2>;
		phandle = <0xf2>;

		spi@0 {
			compatible = "spidev";
			reg = <0x0>;
			spi-max-frequency = <0x2faf080>;

			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,rx-clk-tap-delay = <0x10>;
				nvidia,tx-clk-tap-delay = <0x0>;
			};
		};

		spi@1 {
			compatible = "spidev";
			reg = <0x1>;
			spi-max-frequency = <0x2faf080>;

			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,rx-clk-tap-delay = <0x10>;
				nvidia,tx-clk-tap-delay = <0x0>;
			};
		};
	};


	spi@3230000 {
		compatible = "nvidia,tegra186-spi-slave";
		reg = <0x0 0x3230000 0x0 0x10000>;
		interrupts = <0x0 0x26 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		iommus = <0x2 0x20>;
		dma-coherent;
		dmas = <0x19 0x11 0x19 0x11>;
		dma-names = "rx", "tx";
		spi-max-frequency = <0x3dfd240>;
		nvidia,clk-parents = "pll_p", "clk_m";
		clocks = <0x4 0x89 0x4 0x66 0x4 0xe>;
		clock-names = "spi", "pll_p", "clk_m";
		resets = <0x5 0x5d>;
		reset-names = "spi";
		status = "okay";
		linux,phandle = <0xf4>;
		phandle = <0xf4>;

		spi@0 {
			compatible = "spidev";
			reg = <0x0>;
			spi-max-frequency = <0x2faf080>;

			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,rx-clk-tap-delay = <0x10>;
				nvidia,tx-clk-tap-delay = <0x0>;
			};
		};

		spi@1 {
			compatible = "spidev";
			reg = <0x1>;
			spi-max-frequency = <0x2faf080>;

			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,rx-clk-tap-delay = <0x10>;
				nvidia,tx-clk-tap-delay = <0x0>;
			};
		};
	};
26

Thanks! I have applied those changes and now everything works! I have both I2C and SPI.
I have checked both with spidev-test and with my SPI device, it’s all fine.

So to sum-up:

  • I flashed the default OS freshly downloaded from the Nvidia website on a new SD card
  • started the Jetson Xavier NX dev kit and configured it for both SPI and i2c using jetson-io
  • copied the generated dtb file on a USB drive and stopped the Xavier NX
  • booted the Xavier NX with my custom OS
  • copied the dtb file from the USB drive to the home directory
  • decompiled the dtb file with sudo dtc -I dtb -O dts -o file.dtb decompiled.dts
  • edited the file to replace the “compatible” lines as explained by SchaneCCC in the message above
  • recompiled the dts file into a dtb file with sudo dtc -I dts -O dtb -o new_file.dtb decompiled.dts
  • copied the generated new_file.dtb to /boot/dtb
  • edited the /boot/extlinux/extlinux.conf file to change the FTD line in the JetsonIO part to point towards the new dtb file
  • rebooted

I had a strange issue where I couldn’t ssh into my Xavier NX after the reboot, but I un-plugged the power and plugged it again and the Xavier booted properly and now everything works.

Thanks for the help.

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