Suspend to RAM and hibernate in jetson-tx2 using PSCI

I want to try hibernate feature on jetson-tx2. Before this I want to understand the code flow for normal suspend to ram(STR). From what I see , it uses PSCI 1.0 for suspend to RAM operations. TRM says that some register states(pinmux, GPIO, padctl) are lost when entering SC7 or deep sleep state and these are restored by SC7 exit code. How and where are the registers saved? Any code flow for Suspend to RAM using PSCI?

Is there any way to save registers for suspend to disk(hibernate, STD) and later restore it? In STD case what registers need to be saved?

I found that pinctrl suspend and resume is a dummy function in “drivers/pinctrl/pinctrl-tegra186.c”

static int tegra186_pinctrl_suspend(u32 *pg_data)
        return 0;

static void tegra186_pinctrl_resume(u32 *pg_data)

But when I test STR, it is found to be suspended and later resumed when RTC interrupt is given. How is it getting suspended? And “tegra186_padctl_save and tegra186_padctl_restore” are found in “drivers/pinctrl/pinctrl-tegra186-padctl.c”. Whar does it mean?


Dear IVID,

Suspend/Resume is not totally controlled/monitored by Kernel. There are other SW involved like bpmp.bin, warmboot.bin which plays crutial roles in SC7 path. These SW are not open sourced and are only seen as bin in the flashing directory.
So, its tricky to implement hibernation.


Dear Bibek,

I understand that other PM software come into picture. But tegra is using PSCI firmware for PM activities. Since PSCI is armv8 firmware and open sourced, should not nvidia be open sourcing the softwares you mentioned because obviously nvidia is using PSCI software for Suspend/Resume.

Now for normal suspend to ram, can you give any code flow path that tegra tx2 follows? Like how registers are saved and where are they saved and restored.


hey IVID, have you solved this problem?

Any update with hibernate support?

Hibernation is not supported on Tegra ARM SOC.
So deepest power state is suspend to mem.