TX1 VIN_PWR_BAD# logic level

Hi

we are using TX1 VIN_PWR_BAD# pin in jetson tx1 is a input pin to the processor what is the high and low level for this pin if i am providing VDD_IN as 9v to the processor can i connect a logic 5V signal to enable the pin since it is mentioned that the pin is VDD_IN CMOS how to fix the high and low level to tell the processor the carrier i/p or dc jack power is good what is the level i need to maintain on this line

VIN_PWR_BAD# has pull up in the module which is +5V, no need to add logic for it as it is low enable, which means when VDD_IN is stable, VIN_PWR_BAD# will be pull down, then TX1 power up.

hi

you have mentioned that when VDD_IN is stable, VIN_PWR_BAD# will be pull down

but the timing diagram in OEM design guide page 13
shows that when VDD_IN is stable VIN_PWR_BAD# is high pulled up
since is an active low signal please check confirm

VIN_PWR_BAD# is first pulled down when VDD_IN plug in, and then be high when VDD_IN is stable, and then TX1 can power up.