TX2i GPIO G line is very slow to initialize

Autonomous Machines Jetson & Embedded Systems Jetson TX2
,
1

Hi,

I configured the device tree to control GPIO output and it turns out that GPIO pins G.0-5 won’t be HIGH until ubuntu OS is fully launched. On the other hand, J.0 pin becomes HIGH soon enough in boot procedure.

dts:

	gpio@2200000 {
		g0 {
			gpio-hog;
			gpios = <TEGRA_MAIN_GPIO(G, 0) 0>;
			output-high;
			label = "g0";
			status = "okay";
		};

		j0 {
			gpio-hog;
			gpios = <TEGRA_MAIN_GPIO(J, 0) 0>;
			output-high;
			label = "j0";
			status = "okay";
		};
	};
	sdhci@3440000 {
		status = "disabled";
	};

Besides, G pins cannot be controlled from U-boot while J pins can.

Tegra186 (P2771-0000-500) # gpio toggle J0
gpio: pin J0 (gpio 72) value is 1
 ## -> J0 = HIGH
Tegra186 (P2771-0000-500) # gpio toggle G0
gpio: pin G0 (gpio 48) value is 1
 ## -> G0 = LOW

How can I use GPIO G pins in boot sequence?

3

I have found a statement in Jetson TX2 Series OEM Product Design Guide.

The SD_CARD & SDIO (TX2 4GB/TX2i only) pins are CZ type, but the associated power rails are not enabled at power-on – software enables these at a later time.

What exactly does the “software” mean? linux kernel?

4

hello peroxyacyl,

are you going to control these pin in the u-boot stage,
had you tried to modify the pinmux spreadsheets to update the pin configuration?
please refer to developer guide, Updating the Bootloader Pinmux.
thanks

5

Hello JerryChang,

Thank you for replay.

are you going to control these pin in the u-boot stage

Yes

had you tried to modify the pinmux spreadsheets to update the pin configuration?

Of course I did. attaching excel screenshot.

pinmux_screenshot
pinmux_screenshot2920×194 8.11 KB

6

hello peroxyacyl,

would like to double confirm you’ve use the python tool, $OUT/Linux_for_Tegra/kernel/pinmux/t186/pinmux-dts2cfg.py to output the cfg file,
after that, re-flash the board completely to apply the settings.

7

I used the script and flashed using the cfg files. I checked that a different pad voltage setting caused another behavior. I’m 100% sure about that.

8

hello peroxyacyl,

it’s uboot commands to control GPIO pins in u-boot,
according to tegra186-gpio.h, it’s correct you’re having pin number 48 for TEGRA_MAIN_GPIO(G, 0).

#define TEGRA_MAIN_GPIO(port, offset) \
  	((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)

could you please examine the pin status about, TEGRA_MAIN_GPIO(G, 0).
for example,

Usage:
gpio <input|set|clear|toggle> <pin>
    - input/set/clear/toggle the specified pin
gpio status [-a] [<bank> | <pin>]  - show [all/claimed] GPIOs

besides,
there’s GPIO APIs for cboot, could you please also have a try as below.

CBoot
there’s tegra GPIO driver API for reading a GPIO pin state.
for example,
$L4T_Sources/r32.5.1/Linux_for_Tegra/source/public/cboot/bootloader/partner/common/drivers/gpio/tegrabl_gpio.c
static tegrabl_error_t tegrabl_gpio_read(uint32_t gpio_num, gpio_pin_state_t *state, void *drv_data)