I have questions for Xavier’s pad voltage and PMIC power rail, especially for PCIe (and some GPIO pins).
I read the chapters of “Pad Voltage Configuration” and " PMIC Configuration" in “Jetson develper guide”. And I know that some of Xavier’s pad and pins are configurable to operate at different voltage levels, and the pad voltage configuration MUST match with PMIC power rail configurable. Otherwise, it won’t work or even damage the pins.
What is the pad voltage and PMIC power rail configured for PCIe? I checked OEM doc, OEM says all of the CLKREQ, RESET_n, and WAKE_n signals are “CMOS - 1.8V”. So, I think PCIe is at 1.8V level? Also, based on device-tree, PCIe is set to
vddio-pex-ctl-supply = <&p2888_spmic_sd3>;and
vdd-1v8-ao. So, it seems to be 1.8V based on device-tree as well? However, in the “Jetson_AGX_Series_DevKit_Pinmux_Configuration_Template.xlsm” the pinmux spreadsheet. It has a column for “3.3V Tolerance Enable”. And all PCIe pins are set to “Enable” on “3.3V Tolerance Enable”. Does it mean that it is 3,3V? I am so confused on on that “3.3V Tolerance Enable” in pinmux spreadsheet. What is the meaning of it?
For GPIO6, 7, 8, 9, 10, OEM doc (in CAN chapter) says they are “CMOS 3.3V”. In the pinmux spreadsheet, they are part of the “AO_HV (3.3V)” section. So, I think they are set to 3.3V? However, why in pinmux spreadsheet, there is even no selection option to enable “3.3V Tolerance Enable” for those pins? Also, which part of device-tree set them to be 3.3V? Or they are set in MB1’s pad-voltage config settings?
For “POWER_BTN_N”, OEM doc says it is “Open Drain, 3.3V”. However, in the pinmux spreadsheet, POWER_BTN_N is in “SYS” section (not 3.3V section). Also, its “3.3V Tolerance Enable” column is NOT allowed to be selected for enable!