800x480 Display - PLL D2 Tuning Values

I am trying to get a 800x480 display working. We have narrowed it down to adding a specific PLL tuning line. The PLL in question is PLL D2. Going through the nVidia Tegra K1 Mobile Processor manual we were not able to make sense of the code and relate to to the formula and calculate the appropriate PLL values. Any help with selecting the proper PLL tuning values would be appreciated.

A user was able to make a 800x480 display work as per the following post. His display needs 32MHz pixel clock. Our display requires 33MHz pixel clock.

The relevant line is in:
static struct clk_pll_freq_table tegra_plld2_freq_table;

Our Display Timing:
Pixel Clock: 33 MHz
H Active Pixels: 800
V Active Lines: 480
H Blank: 128
V Blank: 45
H Front Porch: 40
V Front Porch: 13
H Sync Width: 48
V Sync Width: 3

Relevant section for PLL tuning is in the TK1 Manual section 5.6.2 PLL Programming.

We don’t officially cover any modes that are not standard one, especially on TK1.