I just got my boards from the assembly house, and they are not powering-up, so I have to debug.
The power design is with SRC0GS22D.
I see that there’s VCC_SRC_FET, VCC_SRC (~14V), and 5V_AO (5V).
The current consumption is 0 in 4 of 5 boards I got. Pressing the power-switch has no effect.
One board turns on the VDD_5V with no power-button press, and the current is 90mA.
In order to debug, I got to access the power-control signals, but most of them are hidden by the SOM.
Instead of taking wires out, for debug, I would like to remove the SOM, and simulate any signal it is driving.
My understanding is that I only need to drive CARRIER_PWR_ON high.
Is this correct?
Any other suggestion for the debug?
Which signal may cause the board to power-up with no switch-press?
Hi, as you can see in OEM DG, carrier board give power supply to module and generate module_power_on to module after power button pressed so as to power on module, and then module will give carrier_pwr_on to carrier board to power up rails of carrier board. The AC_OK_L is used for auto power on function, for more detail info please refer to OEM DG and reference schematic.
And for those who will try to debug the power-sequence,
I’ll suggest to try shorting carrier_pwr_on to VDD_5V
(not sure - might need to short to higher level - will try and report.)
For now, I’ve left the debug of VIN_PWR_BAD_n, and finally managed to power-up by doing several bypasses:
Today, I’ve found that CARRIER_PWR_ON can be pulled high, by assembly of the option resistor R504 (on 3.3v circuitry).
The D-FF in the ‘simplified button power-on circuitry’ was forcing the BUTTON_POWER_ON# to low, so I’ve disconnected the resistor on the input to the buffer, and shorted to GND.
Now, BUTTON_POWER_ON# is high, and going-low when I press the power-switch.
I have disconnected PSHOLD input of the SRC0, and shorted to 5V_AO - this bypass CARRIER_PWR_ON and VDDIN_PWR_BAD_n, so the power is keeping on after release of the power switch.
Now I have the VDD_5V on, and will go back to debug the bypasses.
I’ve completed the first stage of the bring-up, so here’s my suggestions to the forum:
On first boards, assemble R504 with ~1.5K to set CARRIER_PWR_ON to high level, which will enable the 3.3v and 1.8V.
Note that the ref-design got 20K, which yield a lower-level, not enabling the 1.8 supply)
You should verify having VCC_SRC_FET, then VCC_SRC, then VDD_5V /VDD_3V3 / VDD_1V8.
Once you’ve completed this debug, remove R504, so the 3.3 and 1v8 will not be powered before time.
Note: It might be needed to assemble R17, to force 0 on CVM_PRSNT1.