MODULE_POWER_ON and VIN_PWR_ON are outputs of MCU (EFM8SB1) to XAVIER module for power on，and these two signals are controlled by power button . Now do a test， connect MODULE_POWER_ON and VIN_PWR_ON to 3V3_AO by a 10KΩ registor and also disconnect EFM8SB1, we find the xavier module can work properly. But the timing of this test is different with reference design . Can I apply this design that no MCU and no button to my schematic design ？Please give some advise.
Thanks.
The key point of power sequence is to assert MODULE_POWER_ON after VIN_PWR_BAD released. VIN_PWR_ON is to switch on SYS_VIN_HV and SYS_VIN_MV. The figure 5-2, Power Up Sequence, is for all designs.
How long is the interval required between VIN_PWR_BAD and MODULE_POWER_ON? Can I use VIN _PWR_BAD to be a swtich (usb a nMOS ) to control the on -off state between 3V_A0 with MODULE_POWER_ON ?
No critical timing request between them.
Are you testing on dev kit or prepare to make a custom board? 3V3_AO is carrier board rail which should be up after CARRIER_POWER_ON.
The core sequence is: VIN_PWR_BAD → MODULE_POWER_ON → CARRIER_POWER_ON
3V_AO is powered by 5V_AO that powered by VCC_SRC_FET . As long as the DC is supplied, 3V_AO will be supplied.
Yes as you said, I just mixed it with VDD_3V3. So are you testing on dev kit or prepare to make a custom board? You can do changes only if the power sequence is guaranteed.
One more question, if my design can meet the power up sequence but can not guarantee the power down sequence ，we usually cut the DC directly ，so that will affect the use of module ？
It’s not recommended. Please follow discharge/power loss detection part to make design so as to follow the power down sequence.