Could you please let me know which chips CAN Interfaces (1&2, 3&4, and 5&6) physically connect to? are all of them physically connected to AURIX? or each set is physically connected to Xavier A, B and AURIX respectively?
I guess Xavier A or B can access all CAN interfaces. let me know if not. Could you please provide Linux-based sample C/C++ code that can send/receive CAN commands via the interfaces? It would be better if code is not based on Nvidia DriveWorks library. We have a design requirement of sending/receiving CAN commands by directly talking to CAN Drivers. Please provide steps to set up the CAN interfaces before running the code (in case if these steps cannot be done within C++ code).