We are trying to get display port output working on our own tegra-k1 based board.
We get errors during the display port initialization:
[ 1.350471] tegradc tegradc.0: dp: channel equalization failed
[ 1.350494] tegradc tegradc.0: dp: full lt failed.
[ 1.367654] tegradc tegradc.0: probed
Inside of drivers/video/tegra/dc/dp.c function tegra_dp_channel_eq_status()
I added the following printk() debug:
for (cnt = 0; cnt < n_lanes / 2; cnt++) {
tegra_dc_dp_dpcd_read(dp,
(NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr);
printk( KERN_ERR "mri: check lane %d status, data=0x%x\n",
cnt, data_ptr );
if (!(data_ptr &
(0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) ||
!(data_ptr &
(0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)) ||
!(data_ptr &
(0x1 << NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT)) ||
!(data_ptr &
(0x1 << NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT))) {
ce_done = false;
break;
}
}
The debug output looks like:
[ 1.340003] mri: check lane 0 status, data=0x11
It looks like a successful tegra_dc_dp_dpcd_read( ) status is 0x77, we always read 0x11.
Can you suggest anything to try that may help resolve the problem with
training the display port interface?
The DP to LVDS IC is a NXP PTN3460. The chip uses 2 DP lanes only. We also
have an evaluation board with this chip and connected it to the TEGRA TK1
board using a DP cable soldered to the header and we get the same result.
Connection is as shown in the TEGRA K1 Embedded Platform design Guide
Version 02 page 59.