Display Port Interface Training Fails

We are trying to get display port output working on our own tegra-k1 based board.

We get errors during the display port initialization:

[ 1.350471] tegradc tegradc.0: dp: channel equalization failed
[ 1.350494] tegradc tegradc.0: dp: full lt failed.
[ 1.367654] tegradc tegradc.0: probed

Inside of drivers/video/tegra/dc/dp.c function tegra_dp_channel_eq_status()
I added the following printk() debug:

for (cnt = 0; cnt < n_lanes / 2; cnt++) {
        (NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr);

    printk( KERN_ERR "mri: check lane %d status, data=0x%x\n",
        cnt, data_ptr );

    if (!(data_ptr &
    !(data_ptr &
    !(data_ptr &
    !(data_ptr &
        ce_done = false;

The debug output looks like:
[ 1.340003] mri: check lane 0 status, data=0x11

It looks like a successful tegra_dc_dp_dpcd_read( ) status is 0x77, we always read 0x11.

Can you suggest anything to try that may help resolve the problem with
training the display port interface?

The DP to LVDS IC is a NXP PTN3460. The chip uses 2 DP lanes only. We also
have an evaluation board with this chip and connected it to the TEGRA TK1
board using a DP cable soldered to the header and we get the same result.
Connection is as shown in the TEGRA K1 Embedded Platform design Guide
Version 02 page 59.

We got the displayport working, we switched to a Parade Technologies PS8625
instead of the NXP PTN3460. For some reason the Tegra TK1 has training
problems with the NXP chip. When we use laptops connected to the NXP chip
we do not have problems.

We are also interested in connecting a LVDS display to the TK1. As direct LVDS output does not seem to work (https://devtalk.nvidia.com/default/topic/830827/how-to-interface-lvds-display-on-jetson-tk1-/) we are thinking on using a eDP to LVDS conversion chip like the ones you have tested. By your second reply I think PS8625 would be a better option than PTN3460. However, both are unsupported on kernel version 3.10 provided by nVidia. Which kernel version have you used?

As both chips are eDP standard, we think it would be enough to configure them using i2c channel, so kernel support is not so critical. Are we right or have you found any problems using them?