eDP connection: documentation error in 'Tegra K1 Embedded Platform Guide' ?

While developing an adapter for the eDP port for the Jetson, I consulted 3.5.1, Figure 25 on page 57 of the “Tegra K1 Embedded Platform Guide” (version DG-07508-001v03).

The drawing states that the Negative/Positive differential lines are to be connected swapped to the eDP connector, e.g. LVDS0_TXD0_N is to be connected to LN2_P etc.
For the AUX line, however, the polarity is as expected.

In addition, the LVDS pinout looks like it is connected as expected, with pos/neg connected to pos/neg.

Looking at the “Data Sheet NVIDIA Tegra K1 series processors” (version DS-06742-007v02) under 4.4.3, page 56, it describes the various differential lines, but does not mention that there is a crucial distinction of the meaning of the pos/neg lines if used as eDP interface vs. LVDS - I would’ve expected such mention if it was indeed so.

So I suspect that the “Embedded Platform Guide” is errorneous in this regard. Is this a correct suspicion ?


I have to wonder if perhaps there is an encoding scheme difference between LVDS displays and eDP…if so, this might account for reversal. I’m not a member of VESA (wish I was), so I lack eDP standards documents, but LVDS can be interpreted in multiple ways, which would mean the diagrams could still be correct.

I’m pretty sure when LVDS0_TXD0_N is shown to be connected to LN2_P and so on it’s done by mistake. Direct output shall be connected to direct input and inverted output - to inverted input. Such wrong labelling is also shown at least on Fig 25 and 27.

A note to NVIDIA documentation editors: to avoid confusions please always (!) show “_P” first and then “_N” under it.

Hi hnnr and cioma,

Thank you for pointing out the error in the eDP connection diagram.
We will review and correct the error on the design guide document, and post the new version once the correction done.


Hi @kaycc,

Thanks for looking into the documentation.

While at it, can you verify the Table 2 header pin specification on page 8 and 9 of the “Jetson TK1 Development Specification” (Version 01, November 2014, DA-07507-001) ?

The table seems to be messed up w.r.t some descriptions. For instance Pin #43 is named LVDS_TXD4_N and described as LVDS Clock Lane (+) while #45 is LVDS_TXD4_P and described as LVDS Clock Lane (-).
So the description does not agree with the pin name.

Looking at the schematic (“Jetson TK1 Development Platform Schematics”, Doc number 602-7R375-0000-D00, Rev. 4.04, page 26), it really looks like the LVDS_TXD4_N and _P are at these positions (even though the ‘symmetry’ of the board would disagree with that, in which usually first come the _P followed by the _N) – so it is the descriptions that need to be fixed for #43 and #45.

(The link on http://elinux.org/Jetson/GPIO#Jetson_TK1_GPIO_pinouts is similarly messed up, but that is probably just a copy-paste problem. Then on the eLinux link the pin #33 has a confusing description (negative LVDS and positive eDP) …).

I get the impression, nobody ever tried to connect an LVDS or eDP screen to this; apparently I am the first to notice :)


  1. make sure the eDP documentation in “Tegra TK1 Embedded Platform Guide” is correct.
  2. Double-check and fix description of pins in Table 2 “Jetson TK1 Development Specification”
  3. Possibly fix the information on the external eLinux link.

(Sorry for being so pedantic, but good documentation is important for people using it)