- 1 BSP environment:
jetpack 5.1.1
R35 (release), REVISION: 3.1
AGX orin jetson - 2 Problems:
On our custom board, we have laid out PCIe C4 to operate in a single-lane configuration connecting to an external MCU. However, this setup is not functioning as expected. To ensure PCIe C4 operates correctly in a 1-lane mode (using TX on J34/J35, RX on D32/D33, and CLK on E22/E23),
Should we configure the pinmux to disable the other three lane pins, or should we stick with the default pinmux configuration? Additionally, could you provide some advice on other aspects, such as potential modifications to the Device Tree Source (DTS) or PCIe debugging methods?
Hi,
If the device cannot be flashed/booted, please refer to the page to get uart log from the device:
Jetson/General debug - eLinux.org
And get logs of host PC and Jetson device for reference. If you are using custom board, you can compare uart log of developer kit and custom board to get more information.
Also please check FAQs:
Jetson AGX Orin FAQ
If possible, we would suggest follow quick start in developer guide to re-flash the system:
Quick Start — NVIDIA Jetson Linux Developer Guide 1 documentation
And see if the issue still persists on a clean-flashed system.
Thanks!
C4 is already enabled by default software (pinmux/kernel dtb). If you didn’t change default software, then nothing should be configured.
You shouldn’t configure any “x1” mode either. Our controller supports downward. Default x4 configuration can support x1 too.
hi @WayneWWW
seeing that lots of directories under platform. and find no explanation about them.
what does prometheus and concord mean. we guess that agx orin is under concord platform, is that right?
nvidia/platform/
├── t19x
│ ├── common
│ ├── galen
│ ├── galen-industrial
│ ├── jakku
│ └── mccoy
├── t23x
│ ├── common
│ ├── concord
│ ├── p3768
│ └── prometheus
└── tegra
└── common
Your question has nothing related to original problem. Please file a separate topic is you want to check know how device tree structure is doing.