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How to verify if the hardware modules related to camera data stream acquisition on Orin are functioning properly without a camera?

Autonomous Vehicles DRIVE AGX Orin DRIVE AGX Orin General

deng.shigang July 1, 2025, 2:43am 1

Please provide the following info (tick the boxes after creating this topic):
Software Version
[*] DRIVE OS 6.0.10.0
DRIVE OS 6.0.8.1
DRIVE OS 6.0.6
DRIVE OS 6.0.5
DRIVE OS 6.0.4 (rev. 1)
DRIVE OS 6.0.4 SDK
other

Target Operating System
[*] Linux
QNX
other

Hardware Platform
DRIVE AGX Orin Developer Kit (940-63710-0010-300)
DRIVE AGX Orin Developer Kit (940-63710-0010-200)
DRIVE AGX Orin Developer Kit (940-63710-0010-100)
DRIVE AGX Orin Developer Kit (940-63710-0010-D00)
DRIVE AGX Orin Developer Kit (940-63710-0010-C00)
DRIVE AGX Orin Developer Kit (not sure its number)
other

SDK Manager Version
2.1.0
other

Host Machine Version
native Ubuntu Linux 20.04 Host installed with SDK Manager
native Ubuntu Linux 20.04 Host installed with DRIVE OS Docker Containers
native Ubuntu Linux 18.04 Host installed with DRIVE OS Docker Containers
other

Issue Description

How to verify if the hardware modules related to camera data stream acquisition on Orin are functioning properly without a camera?

Error String
< Please provide just the error messages here >

Logs
Provide logs in text box instead of image

Please paste the complete application log here. If there are multiple logs, please use multiple text box

SivaRamaKrishnaNV July 1, 2025, 4:24am 3

Dear @deng.shigang ,
Did you try MAX96712_RAW12_TPG_CPHY_x platform config with nvsipl_camera?

deng.shigang July 1, 2025, 5:54am 4

I have tried again and the results are as follows. Does this mean that there are no issues with the camera related hardware on ORIN?
How is platform config determined in the nvsiplcamera program? How to obtain which platform config can be used?

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config “V728S1-120V1-FWC_CPHY_x4” --link-enable-masks “0x0001 0x0000 0x0000 0x0000”
[sudo] password for zhangzs:
Pipeline: 0 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
Pipeline: 0 ISP Output: 1 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
Pipeline: 0 ISP Output: 2 is using RGBA PACKED FLOAT16 PL SENSOR_RGBA
MAX96712: Revision 5 detected
MAX96712 Link 0: PHY optimization was enabled
MAX96717F: Revision 2
MAX96717F: Revision 4
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$

SivaRamaKrishnaNV July 1, 2025, 6:09am 5

Dear @deng.shigang ,
May I now the used camera module? Supported sensors is listed in DRIVE AGX Orin Sensors & Accessories | NVIDIA Developer

deng.shigang July 1, 2025, 6:54am 7

is： OmniVision OX08D10-EXAE-AA1C

SivaRamaKrishnaNV July 1, 2025, 7:07am 8

Dear @deng.shigang ,
Did you get the needed files and steps to bring up your camera from omnivision?

deng.shigang July 1, 2025, 7:09am 9

Yes, but we are unable to connect the camera, so we want to rule out the possibility that some of the Orin hardware is faulty

deng.shigang July 1, 2025, 7:20am 10

error：
zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_R1D_CPHY_x2 --link-enable-mas
ks 0x0001 0x0000 0x0000 0x0000 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

SivaRamaKrishnaNV July 1, 2025, 7:39am 11

Could you share nvsipl_camera -h?

Also, share sudo ./nvsipl_camera --platform-config "MAX96712_RAW12_TPG_DPHY_x4" --link-enable-masks "0x0001 0x0000 0x0000 0x0000" --enableRawOutput --disableISP0Output --disableISP1Output --disableISP2Output --showfps output?

deng.shigang July 1, 2025, 7:41am 12

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ ./nvsipl_camera -h
Usage:
-h or --help :Prints this help
-c or --platform-config ‘name’ :Platform configuration. Supported values
R0SIM623S3RU1197NB1_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
R0SIM623S3RU1197NB1_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
R0SIM623S3RU1197NB1_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
R0SIM623S3RU1197NB1_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
R0SIM623S3RU1197NB1_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
R0SIM623S3RU1197NB1_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
R0SIM623S4RU1197NB2_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
R0SIM623S4RU1197NB2_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
R0SIM623S4RU1197NB2_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
R0SIM623S4RU1197NB2_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
R0SIM623S4RU1197NB2_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
R0SIM623S4RU1197NB2_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
R0SIM623S4RU1197NB2_REC_CPHY_x2_TPG:IMX623 RGGB module in 2 lane CPHY, TPG mode
R0SIM623S5RU1197NB3_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
R0SIM623S5RU1197NB3_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
R0SIM623S5RU1197NB3_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
R0SIM623S5RU1197NB3_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
R0SIM623S5RU1197NB3_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
R0SIM623S5RU1197NB3_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
R0SIM623S5RU1197NB3_REC_CPHY_x2_TPG:IMX623 RGGB module in 2 lane CPHY, TPG mode
F2O05B1S1DHU1170NB10_CPHY_x2 :F2O05B1S1DHU1170NB10 module in 2 lane CPHY mode
F2O05B1S1DHU1170NB10_CPHY_x4 :F2O05B1S1DHU1170NB10 module in 4 lane CPHY mode
V1SIM623S3RU3200NB20_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623S3RU3200NB20_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
V1SIM623S3RU3200NB20_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
V1SIM623S3RU3200NB20_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
V1SIM623S3RU3200NB20_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623S3RU3200NB20_R_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623S3RU3200NB20_R_CPHY_x4 :IMX623 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM623S3RU3200NB20_R_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623S4RU5195NB3_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623S4RU5195NB3_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
V1SIM623S4RU5195NB3_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
V1SIM623S4RU5195NB3_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623S4RU5195NB3_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
V1SIM623S4RU5195NB3_R_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623S4RU5195NB3_R_CPHY_x4 :IMX623 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM623S4RU5195NB3_R_REC_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623S5RU5195NC0_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623S5RU5195NC0_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
V1SIM623S5RU5195NC0_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
V1SIM623S5RU5195NC0_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
V1SIM623S5RU5195NC0_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623S5RU5195NC0_R_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623S5RU5195NC0_R_CPHY_x4 :IMX623 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM623S5RU5195NC0_R_REC_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623SARU6195NC1_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623SARU6195NC1_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
V1SIM623SARU6195NC1_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
V1SIM623SARU6195NC1_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
V1SIM623SARU6195NC1_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623SARU6195NC1_R_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623SARU6195NC1_R_CPHY_x4 :IMX623 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM623SARU6195NC1_R_REC_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623S5RU6195NC1_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623S5RU6195NC1_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
V1SIM623S5RU6195NC1_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
V1SIM623S5RU6195NC1_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
V1SIM623S5RU6195NC1_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623S5RU6195NC1_R_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623S5RU6195NC1_R_CPHY_x4 :IMX623 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM623S5RU6195NC1_R_REC_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623MPRU7200NC2_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623MPRU7200NC2_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
V1SIM623MPRU7200NC2_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
V1SIM623MPRU7200NC2_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
V1SIM623MPRU7200NC2_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V1SIM623MPRU7200NC2_R_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM623MPRU7200NC2_R_CPHY_x4 :IMX623 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM623MPRU7200NC2_R_REC_CPHY_x2 :IMX623 RGGB module with 180 degree rotation in 2 lane CPHY mode
F2O05B1B1DMU1058NB10_CPHY_x2 :F2O05B1B1DMU1058NB10 module in 2 lane CPHY mode
F2O05B1B1DMU1058NB10_CPHY_x4 :F2O05B1B1DMU1058NB10 module in 4 lane CPHY mode
F008A120RM0AV2_CPHY_x2 :F008A120RM0A 24BIT RGGB module in 2 lane CPHY mode
F008A120RM0AV2_CPHY_x2_TPG :F008A120RM0A 24BIT RGGB module in 2 lane CPHY, TPG mode
F008A120RM0AV2_CPHY_x4 :F008A120RM0A 24BIT RGGB module in 4 lane CPHY mode
F008A120RM0AV2_CPHY_x4_TPG :F008A120RM0A 24BIT RGGB module in 4 lane CPHY, TPG mode
F008A120RM0AV2_REC_CPHY_x2 :F008A120RM0A 24BIT RGGB module in 2 lane CPHY mode
C2SIM623S2RU1195NB20_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
C2SIM623S2RU1195NB20_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
C2SIM623S2RU1195NB20_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
C2SIM623S2RU1195NB20_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
C2SIM623S2RU1195NB20_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
C2SIM623S2RU1195NB20_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
LI-OV2311-VCSEL-GMSL2-60H_DPHY_x4 :LI-OV2311-VCSEL-GMSL2-60H module in 4 lane DPHY mode
LI-OV2311-VCSEL-GMSL2-60H_DPHY_x2 :LI-OV2311-VCSEL-GMSL2-60H module in 2 lane DPHY mode
LI-OV2311-VCSEL-GMSL2-60H_L_DPHY_x4:LI-OV2311-VCSEL-GMSL2-60H_L module in 4 lane DPHY mode
LI-OV2311-VCSEL-GMSL2-60H_L_DPHY_x2:LI-OV2311-VCSEL-GMSL2-60H_L module in 2 lane DPHY mode
LI-OV2311-VCSEL-GMSL2-60H_DPHY_x2_TPG:LI-OV2311-VCSEL-GMSL2-60H module in 2 lane DPHY, TPG mode
V728S1-120V0_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V728S1-120V0_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V728S1-120V0_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V728S1-120V0_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V728S1-120V1-FWC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V728S1-120V1-FWC_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V728S1-120V1-FWC_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V728S1-120V1-FWC_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V728S1-120V1-SCF_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V728S1-120V1-SCF_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V728S1-120V1-SCF_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V728S1-120V1-SCF_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V728S1-070V1-SCR_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V728S1-070V1-SCR_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V728S1-070V1-SCR_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V728S1-070V1-SCR_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V728S1-030V1-FTC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V728S1-030V1-FTC_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V728S1-030V1-FTC_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V728S1-030V1-FTC_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V728S1-030V1-RC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V728S1-030V1-RC_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V728S1-030V1-RC_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V728S1-030V1-RC_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S2RU2030NB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S2RU2030NB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S2RU2030NB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU2030NB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S2RU4070HB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S2RU4070HB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S2RU4070HB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU4070HB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S2RU4120NB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S2RU4120NB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S2RU4120NB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU4120NB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S2RU4120HB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S2RU4120HB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S2RU4120HB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU4120HB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S2RU2030NB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU4070HB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU4120NB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU4120HB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU4070HB20_R_CPHY_x4 :IMX728 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM728S2RU4070HB20_R_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728S2RU4070HB20_R_REC_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728S1RU3120NB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S1RU3120NB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S1RU3120NB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S1RU3120NB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S1RU3070HB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S1RU3070HB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S1RU3070HB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S1RU3070HB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S1RU3030NB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S1RU3030NB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S1RU3030NB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S1RU3030NB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S1RU3120NB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S1RU3070HB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S1RU3030NB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S1RU3070HB20_R_CPHY_x4 :IMX728 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM728S1RU3070HB20_R_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728S1RU3070HB20_R_REC_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728S2RU1030NB30_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S2RU3070HB30_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU1030NB30_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S2RU1030NB30_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU1030NB30_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU1030NB30_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S2RU3070HB30_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S2RU3070HB30_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S2RU3070HB30_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU3070HB30_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S2RU3120NB30_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S2RU3120NB30_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S2RU3120NB30_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU3120NB30_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S2RU3120HB30_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S2RU3120HB30_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S2RU3120HB30_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU3120HB30_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S2RU1030NB30_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU3070HB30_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU3120NB30_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU3120HB30_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S2RU3070HB30_R_CPHY_x4 :IMX728 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM728S2RU3070HB30_R_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728S2RU3070HB30_R_REC_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728S3RU2030NC00_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S3RU4070HC00_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU2030NC00_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S3RU2030NC00_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU2030NC00_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU2030NC00_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S3RU4070HC00_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S3RU4070HC00_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S3RU4070HC00_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4070HC00_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S3RU4120NC00_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S3RU4120NC00_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S3RU4120NC00_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4120NC00_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S3RU4120HC00_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S3RU4120HC00_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S3RU4120HC00_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4120HC00_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S3RU2030NC00_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4070HC00_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4120NC00_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4120HC00_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4070HC00_R_CPHY_x4 :IMX728 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM728S3RU4070HC00_R_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728S3RU4070HC00_R_REC_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728SARU3030NC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4070HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030NC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU3030NC10_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030NC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030NC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU3030HC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4070HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030HC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU3030HC10_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030HC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030HC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU4070HC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4070HC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU4070HC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4070HC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU4120NC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4120NC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU4120NC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120NC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU4120HC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4120HC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU4120HC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120HC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU3030NC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4070HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120NC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4070HC10_R_CPHY_x4 :IMX728 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM728SARU4070HC10_R_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728SARU4070HC10_R_REC_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728S3RU3030NC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S3RU4070HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU3030NC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S3RU3030NC10_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU3030NC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU3030NC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S3RU3030HC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S3RU4070HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU3030HC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S3RU3030HC10_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU3030HC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU3030HC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S3RU4070HC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S3RU4070HC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S3RU4070HC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4070HC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S3RU4120NC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S3RU4120NC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S3RU4120NC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4120NC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S3RU4120HC10_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728S3RU4120HC10_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728S3RU4120HC10_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4120HC10_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728S3RU3030NC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU3030HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4070HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4120NC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4120HC10_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728S3RU4070HC10_R_CPHY_x4 :IMX728 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM728S3RU4070HC10_R_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728S3RU4070HC10_R_REC_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728SARU3030NC20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4070HC20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030NC20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU3030NC20_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030NC20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030NC20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU3030HC20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4070HC20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030HC20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU3030HC20_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030HC20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030HC20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU4070HC20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4070HC20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU4070HC20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4070HC20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU4120NC20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4120NC20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU4120NC20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120NC20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU4120HC20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4120HC20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU4120HC20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120HC20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU3030NC20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030HC20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4070HC20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120NC20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120HC20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4070HC20_R_CPHY_x4 :IMX728 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM728SARU4070HC20_R_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728SARU4070HC20_R_REC_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728SARU3030NC40_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4070YC40_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030NC40_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU3030NC40_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030NC40_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030NC40_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU3030YC40_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4070YC40_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030YC40_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU3030YC40_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030YC40_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030YC40_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU4070YC40_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4070YC40_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU4070YC40_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4070YC40_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU4120NC40_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4120NC40_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU4120NC40_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120NC40_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU4120YC40_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728SARU4120YC40_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728SARU4120YC40_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120YC40_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728SARU3030NC40_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU3030YC40_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4070YC40_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120NC40_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4120YC40_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728SARU4070YC40_R_CPHY_x4 :IMX728 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM728SARU4070YC40_R_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728SARU4070YC40_R_REC_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728MPRU3030ND1_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728MPRU4070HD1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU3030ND1_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728MPRU3030ND1_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU3030ND1_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU3030ND1_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728MPRU3030HD1_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728MPRU4070HD1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU3030HD1_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728MPRU3030HD1_DPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU3030HD1_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU3030HD1_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728MPRU4070HD1_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728MPRU4070HD1_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728MPRU4070HD1_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU4070HD1_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728MPRU4120ND1_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728MPRU4120ND1_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728MPRU4120ND1_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU4120ND1_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728MPRU4120HD1_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
V1SIM728MPRU4120HD1_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
V1SIM728MPRU4120HD1_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU4120HD1_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
V1SIM728MPRU3030ND1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU3030HD1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU4070HD1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU4120ND1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU4120HD1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
V1SIM728MPRU4070HD1_R_CPHY_x4 :IMX728 RGGB module with 180 degree rotation in 4 lane CPHY mode
V1SIM728MPRU4070HD1_R_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
V1SIM728MPRU4070HD1_R_REC_CPHY_x2 :IMX728 RGGB module with 180 degree rotation in 2 lane CPHY mode
FLC_DMS_CUST1v2 :FLC + DMS profile, linux only
V623S2-195V1-SVS_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
V623S2-195V1-SVS_CPHY_x2_TPG :IMX623 RGGB module in 2 lane CPHY, TPG mode
V623S2-195V1-SVS_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
V623S2-195V1-SVS_CPHY_x4_TPG :IMX623 RGGB module in 4 lane CPHY, TPG mode
OX08D10-EXAE-AA1C_R1D_F_CPHY_x2 :OX08D10-EXAE-AA1C_R1D_F module in 2 lane CPHY mode
OX08D10-EXAE-AA1C_R1D_F_CPHY_x2_TPG:OX08D10-EXAE-AA1C_R1D_F module in 2 lane CPHY, TPG mode
OX08D10-EXAE-AA1C_R1D_F_CPHY_x4 :OX08D10-EXAE-AA1C_R1D_F module in 4 lane CPHY mode
OX08D10-EXAE-AA1C_R1D_F_CPHY_x4_TPG:OX08D10-EXAE-AA1C_R1D_F module in 4 lane CPHY, TPG mode
OX08D10-EXAE-AA1C_R1D_MF_CPHY_x2 :OX08D10-EXAE-AA1C_R1D_MF module in 2 lane CPHY mode
OX08D10-EXAE-AA1C_R1D_MF_CPHY_x2_TPG:OX08D10-EXAE-AA1C_R1D_MF module in 2 lane CPHY, TPG mode
OX08D10-EXAE-AA1C_R1D_MF_CPHY_x4 :OX08D10-EXAE-AA1C_R1D_MF module in 4 lane CPHY mode
OX08D10-EXAE-AA1C_R1D_MF_CPHY_x4_TPG:OX08D10-EXAE-AA1C_R1D_MF module in 4 lane CPHY, TPG mode
OX08D10-EXAE-AA1C_R1D_M_CPHY_x2 :OX08D10-EXAE-AA1C_R1D_M module in 2 lane CPHY mode
OX08D10-EXAE-AA1C_R1D_M_CPHY_x2_TPG:OX08D10-EXAE-AA1C_R1D_M module in 2 lane CPHY, TPG mode
OX08D10-EXAE-AA1C_R1D_M_CPHY_x4 :OX08D10-EXAE-AA1C_R1D_M module in 4 lane CPHY mode
OX08D10-EXAE-AA1C_R1D_M_CPHY_x4_TPG:OX08D10-EXAE-AA1C_R1D_M module in 4 lane CPHY, TPG mode
OX08D10-EXAE-AA1C_R1D_CPHY_x2 :OX08D10-EXAE-AA1C_R1D module in 2 lane CPHY mode
OX08D10-EXAE-AA1C_R1D_CPHY_x2_TPG :OX08D10-EXAE-AA1C_R1D module in 2 lane CPHY, TPG mode
OX08D10-EXAE-AA1C_R1D_CPHY_x4 :OX08D10-EXAE-AA1C_R1D module in 4 lane CPHY mode
OX08D10-EXAE-AA1C_R1D_CPHY_x4_TPG :OX08D10-EXAE-AA1C_R1D module in 4 lane CPHY, TPG mode
MAX96712_2880x1860_YUV_8_TPG_DPHY_x2:MAX96712 YUV 8-bit TPG in 2 lane DPHY mode
MAX96712_2880x1860_YUV_8_TPG_DPHY_x4:MAX96712 YUV 8-bit TPG in 4 lane DPHY mode
MAX96712_2880x1860_YUV_8_TPG_CPHY_x2:MAX96712 YUV 8-bit TPG in 2 lane CPHY mode
MAX96712_2880x1860_YUV_8_TPG_CPHY_x4:MAX96712 YUV 8-bit TPG in 4 lane CPHY mode
MAX96712_RAW12_TPG_DPHY_x2 :MAX96712 RAW12 TPG in 2 lane DPHY mode
MAX96712_RAW12_TPG_DPHY_x4 :MAX96712 RAW12 TPG in 4 lane DPHY mode
MAX96712_RAW12_TPG_CPHY_x2 :MAX96712 RAW12 TPG in 2 lane CPHY mode
MAX96712_RAW12_TPG_CPHY_x2_b :MAX96712 RAW12 TPG in 2 lane CPHY mode
MAX96712_RAW12_TPG_CPHY_x4 :MAX96712 RAW12 TPG in 4 lane CPHY mode
MAX96712_RGB_TPG_DPHY_x2 :MAX96712 RGB TPG in 2 lane DPHY mode
MAX96712_RGB_TPG_DPHY_x4 :MAX96712 RGB TPG in 4 lane DPHY mode
MAX96712_RGB_TPG_CPHY_x2 :MAX96712 RGB TPG in 2 lane CPHY mode
MAX96712_RGB_TPG_CPHY_x4 :MAX96712 RGB TPG in 4 lane CPHY mode
MAX96712_RAW12_TPG_REC_DPHY_x2 :MAX96712 RAW12 TPG in 2 lane DPHY mode
MAX96712_RAW12_TPG_REC_CPHY_x2 :MAX96712 RAW12 TPG in 2 lane CPHY mode
MAX96712_TPG_USECASE1_CPHY_x4 :MAX96712 TPG USECASE1 in 4 lane CPHY mode
MAX96712_TPG_USECASE2_CPHY_x4 :MAX96712 TPG USECASE2 in 4 lane CPHY mode
MAX96712_YUV_8_TPG_DPHY_x2 :MAX96712 YUV 8-bit TPG in 2 lane DPHY mode
MAX96712_YUV_8_TPG_DPHY_x4 :MAX96712 YUV 8-bit TPG in 4 lane DPHY mode
MAX96712_YUV_8_TPG_CPHY_x2 :MAX96712 YUV 8-bit TPG in 2 lane CPHY mode
MAX96712_YUV_8_TPG_CPHY_x4 :MAX96712 YUV 8-bit TPG in 4 lane CPHY mode
MAX96712_YUVSP_8_TPG_CPHY_x4 :MAX96712 YUV 8-bit TPG in 4 lane CPHY mode
MAX96712_YUVSP_10_TPG_CPHY_x4 :MAX96712 YUV 10-bit TPG in 4 lane CPHY mode
IMX728_FPDLINK_RGGB_CPHY_x4 :IMX728 FPD-Link RGGB module in 4 lane CPHY mode
R0SIM728S2RU2120NB1_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
R0SIM728S2RU2120NB1_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
R0SIM728S2RU2120NB1_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S2RU2120NB1_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
R0SIM728S2RU2120NB1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S2RU1070NB1_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
R0SIM728S2RU1070NB1_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
R0SIM728S2RU1070NB1_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S2RU1070NB1_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
R0SIM728S2RU1070NB1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S2RU2030NB1_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
R0SIM728S2RU2030NB1_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
R0SIM728S2RU2030NB1_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S2RU2030NB1_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
R0SIM728S2RU2030NB1_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S3RU2120NB2_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
R0SIM728S3RU2120NB2_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
R0SIM728S3RU2120NB2_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S3RU2120NB2_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
R0SIM728S3RU2120NB2_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S3RU2120NB2_REC_CPHY_x2_TPG:IMX728 RGGB module in 2 lane CPHY, TPG mode
R0SIM728S3RU1070NB2_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
R0SIM728S3RU1070NB2_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
R0SIM728S3RU1070NB2_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S3RU1070NB2_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
R0SIM728S3RU1070NB2_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S3RU1070NB2_REC_CPHY_x2_TPG:IMX728 RGGB module in 2 lane CPHY, TPG mode
R0SIM728S3RU2030NB2_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
R0SIM728S3RU2030NB2_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
R0SIM728S3RU2030NB2_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S3RU2030NB2_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
R0SIM728S3RU2030NB2_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
R0SIM728S3RU2030NB2_REC_CPHY_x2_TPG:IMX728 RGGB module in 2 lane CPHY, TPG mode
AR0820C70FOV_24BIT_RGGB_CPHY_x2 :AR0820C70FOV_24BIT(B0) RGGB module in 2 lane CPHY mode
AR0820C70FOV_24BIT_RGGB_CPHY_x2_TPG:AR0820C70FOV_24BIT(B0) RGGB module in 2 lane CPHY, TPG mode
VC0820C030R24_CPHY_x2 :AR0820 30FOV 24BIT RGGB module in 2 lane CPHY mode
VC0820C030R24_CPHY_x2_TPG :AR0820 30FOV 24BIT RGGB module in 2 lane CPHY, TPG mode
VC0820C070R24_CPHY_x2 :AR0820 70FOV 24BIT RGGB module in 2 lane CPHY mode
VC0820C070R24_CPHY_x2_TPG :AR0820 70FOV 24BIT RGGB module in 2 lane CPHY, TPG mode
R0OOX05B1CHU1170NB10_CPHY_x2 :R0OOX05B1CHU1170NB10 module in 2 lane CPHY mode
R0OOX05B1CHU1170NB10_CPHY_x2_TPG :R0OOX05B1CHU1170NB10 module in 2 lane CPHY, TPG mode
R0OOX05B1CHU1170NB10_CPHY_x4 :R0OOX05B1CHU1170NB10 module in 4 lane CPHY mode
R0OOX05B1CHU1170NB10_CPHY_x4_TPG :R0OOX05B1CHU1170NB10 module in 4 lane CPHY, TPG mode
R0OOX05B1CHU1170NB20_CPHY_x2 :R0OOX05B1CHU1170NB20 module in 2 lane CPHY mode
R0OOX05B1CHU1170NB20_CPHY_x2_TPG :R0OOX05B1CHU1170NB20 module in 2 lane CPHY, TPG mode
R0OOX05B1CHU1170NB20_CPHY_x4 :R0OOX05B1CHU1170NB20 module in 4 lane CPHY mode
R0OOX05B1CHU1170NB20_CPHY_x4_TPG :R0OOX05B1CHU1170NB20 module in 4 lane CPHY, TPG mode
R0OOX05B1CHU1170NB20_REC_CPHY_x2 :R0OOX05B1CHU1170NB20 module in 2 lane CPHY mode
I0OO23111CML1050NB10_CPHY_x4 :I0OO23111CML1050NB10 module in 4 lane cphy mode
I0OO23111CML1050NB10_CPHY_x2 :I0OO23111CML1050NB10 module in 2 lane cphy mode
I0OO23111CML1050NB10_30FPS_CPHY_x4 :I0OO23111CML1050NB10 module in 4 lane cphy mode
I0OO23111CML1050NB10_30FPS_CPHY_x2 :I0OO23111CML1050NB10 module in 2 lane cphy mode
I0OO23111CML1050NB10_CPHY_x2_TPG :I0OO23111CML1050NB10 module in 2 lane cphy, TPG mode
LI-OV2311-VCSEL-GMSL2-55H_CPHY_x4 :LI-OV2311-VCSEL-GMSL2-55H module in 4 lane cphy mode
LI-OV2311-VCSEL-GMSL2-55H_CPHY_x2 :LI-OV2311-VCSEL-GMSL2-55H module in 2 lane cphy mode
LI-OV2311-VCSEL-GMSL2-55H_L_CPHY_x4:LI-OV2311-VCSEL-GMSL2-55H_L module in 4 lane cphy mode
LI-OV2311-VCSEL-GMSL2-55H_L_CPHY_x2:LI-OV2311-VCSEL-GMSL2-55H_L module in 2 lane cphy mode
LI-OV2311-VCSEL-GMSL2-55H_CPHY_x2_TPG:LI-OV2311-VCSEL-GMSL2-55H module in 2 lane cphy, TPG mode
I0OO23111CML1050NB10_REC_CPHY_x2 :I0OO23111CML1050NB10 module in 2 lane cphy mode
LI-OV2311-VCSEL-GMSL2-55H_REC_CPHY_x2:LI-OV2311-VCSEL-GMSL2-55H module in 2 lane cphy mode
C2SIM728S2RU1120NB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
C2SIM728S2RU1120NB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
C2SIM728S2RU1120NB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
C2SIM728S2RU1120NB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
C2SIM728S2RU1120NB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
C2SIM728S2RU1070HB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
C2SIM728S2RU1070HB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
C2SIM728S2RU1070HB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
C2SIM728S2RU1070HB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
C2SIM728S2RU1070HB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
C2SIM728S2RU1070NB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
C2SIM728S2RU1070NB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
C2SIM728S2RU1070NB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
C2SIM728S2RU1070NB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
C2SIM728S2RU1070NB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
C2SIM728S2RU1030NB20_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
C2SIM728S2RU1030NB20_CPHY_x4_TPG :IMX728 RGGB module in 4 lane CPHY, TPG mode
C2SIM728S2RU1030NB20_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
C2SIM728S2RU1030NB20_CPHY_x2_TPG :IMX728 RGGB module in 2 lane CPHY, TPG mode
C2SIM728S2RU1030NB20_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
SIM_IMX728_120FOV_30FPS_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
SIM_IMX728_120FOV_30FPS_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
SIM_IMX728_70FOV_30FPS_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
SIM_IMX728_70FOV_30FPS_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
SIM_IMX728_30FOV_30FPS_CPHY_x4 :IMX728 RGGB module in 4 lane CPHY mode
SIM_IMX728_30FOV_30FPS_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
SIM_IMX728_120FOV_30FPS_REC_CPHY_x2:IMX728 RGGB module in 2 lane CPHY mode
SIM_IMX728_70FOV_30FPS_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
SIM_IMX728_30FOV_30FPS_REC_CPHY_x2 :IMX728 RGGB module in 2 lane CPHY mode
IMX390_CUST1_V2_F200_RGGB_DPHY_x2 :IMX390_C_3461 RGGB module in 2 lane DPHY mode
IMX390_CUST1_V2_F200_RGGB_DPHY_x2_TPG:IMX390_C_3461 RGGB module in 4 lane DPHY, TPG mode
IMX390_CUST1_V2_F200_RGGB_DPHY_x4 :IMX390_C_3461 RGGB module in 4 lane DPHY mode
IMX390_CUST1_V2_F200_RGGB_DPHY_x4_TPG:IMX390_C_3461 RGGB module in 4 lane DPHY, TPG mode
IMX390_CUST1_V2_F200_RGGB_CPHY_x4 :IMX390_C_3461 RGGB module in 4 lane CPHY mode
IMX390_CUST1_V2_F200_RGGB_CPHY_x2 :IMX390_C_3461 RGGB module in 2 lane CPHY mode
IMX390_CUST1_V2_F200_RGGB_CPHY_x2_TPG:IMX390_C_3461 RGGB module in 4 lane CPHY, TPG mode
IMX390_CUST1_V2_F200_RGGB_CPHY_x4_TPG:IMX390_C_3461 RGGB module in 4 lane CPHY, TPG mode
SIM_IMX623_30FPS_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
SIM_IMX623_30FPS_CPHY_x4 :IMX623 RGGB module in 4 lane CPHY mode
SIM_IMX623_30FPS_REC_CPHY_x2 :IMX623 RGGB module in 2 lane CPHY mode
DS90UB971_RAW12_TPG_DPHY_x4 :DS90UB971 RAW12 TPG in 4 lane DPHY mode
DS90UB971_RAW12_TPG_CPHY_x4 :DS90UB971 RAW12 TPG in 4 lane DPHY mode
-m or --link-enable-masks ‘masks’ :Enable masks for links on each deserializer connected to CSI
:masks is a list of masks for each deserializer.
:Eg: ‘0x0000 0x1101 0x0000 0x0000’ disables all but links 0, 2 and 3 on CSI-CD intrface
-r or --runfor :Exit application after n seconds (also disables runtime menu)
-v or --verbosity :Set verbosity
:Supported values (default: 1)
: 0 (None)
: 1 (Errors)
: 2 (Warnings and above)
: 3 (Infos and above)
: 4 (Debug and above)
-t or --test-config-file :Set custom platform config json file
-l or --list-configs :List configs from file specified via -t or --test-config-file
-R or --enableRawOutput :Enable the Raw output
-0 or --disableISP0Output :Disable the ISP0 output
-1 or --disableISP1Output :Disable the ISP1 output
-2 or --disableISP2Output :Disable the ISP2 output
-s or --showfps :Show FPS (frames per second) every 2 seconds
-M or --showmetadata :Show Metadata when RAW output is enabled
-p or --plugin :Auto Control Plugin. Supported types (default: If nito available 0 else 1)
: 0 Nvidia AE/AWB Plugin
: 1 Custom Plugin
-a or --autorecovery :Recover deserializer link failure automatically
-C or --nvsci :Use NvSci for communication and synchronization
-k or --profile :Dump profiling timestamps in file-prefix_cam_x_out_y.csv file
-N or --nito :Path to folder containing NITO files
-O or --icrop ‘y+h’ :Specifies the cropping at the input in the format ‘y+h’
-e or --showEEPROM :Show EEPROM data
-I or --ignoreError :Ignore the fatal error
-o or --enableStatsOverrideTest :Enable ISP statistics settings override
-u or --disableSubframe :Disable Subframe feature
-S or --enablePassive :Enable passive mode
-f or --filedump-prefix ‘str’ :Dump RAW file with filename prefix ‘str’ when RAW output is enabled.
-K or --skipFrames :Number of frames to skip before writing to file
-W or --writeFrames :Number of frames to write to file
-Z or --disableAuth :Forcefully disable authentication for all camera sensors.
-w or --camRecCfg :Recorder configuration
:0 - No recorder support(default)
:1 - Recorder support with the cable version 1
:2 - Recorder support with the cable version 2
-T or --twoPassISP :Process the same captured frames through two different ISP pipelines
:Set value to zero to send frames from pipeline with higher ID to pipeline with lower ID
:Use any nonzero value to send frames from pipeline with lower ID to pipeline with higher ID
:Use comma separator for multiple files.
-z or --writeEEPROM :Write EEPROM data
-D or --syncGPIOIdxDes ‘gpios’ :GPIO index of the deserializer for FRSYNC signal. Applicable only for the specific board
:GPIO index is a list of GPIOs for each deserializer.
:Eg: ‘2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 4’ use GPIO 4 for the link 1 and 3 on CSI-GH interface and GPIO 2 is used for other links
:Eg: ‘1 2 3’ selects the selection index 1 for the multiplxer on CSI-CD, the selection index 2 for the multiplxer on CSI-EF, the selection index 3 for the multiplxer on CSI-GH,
-U or --syncMuxSelDes ‘Indexes’ :Selection index to the multiplexer. Applicable only for the specific board
:Index is a list of selection index for each deserializer.
-E or --setSensorCharMode :Set sensor in characterization mode with exposure number.
-d or --num-disp :Number of displays
:Number of available displays: 1
-p or --disp-win-pos ‘rect’ :Display position, where rect is x0, y0, width, height
-A or --autoLED :Enable automatic LED control, specifically for AR0234
-G or --showNitoMetadata :Get and display NITO Metadata (ID, dataHash, schemaHash) from NITO file(s) to console.
-g or --numParameterSetsInNITO :Number of parameter sets in NITO file. Defaults to 10, must be >=1. Use if expecting >10 parameter sets in NITO file(s).
-i or --input-raw-files <file1[,file2]…> :Set input RAW files for simulator mode testing.
-F or --fsyncGroupStartTime ‘group ticks’ :Group ID and start time in tsc ticks to be programmed.
:All fsync signal generator in group will start at specified start time.
:Eg: ‘group_id start_time_in_tsc_ticks’.
zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$

deng.shigang July 1, 2025, 7:42am 13

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config “MAX96712_RAW12_TPG_DPHY_x4” --link-enable-masks “0x0001 0x0000 0x0000 0x0000” --enableRawOutput --disableISP0Output --disableISP1Output --disableISP2Output --showfps
MAX96712: Revision 5 detected
Enter ‘les’ followed by sensor ID to enable LED
Enter ‘lds’ followed by sensor ID to disable LED
Enter ‘dl’ followed by sensor ID to disable the link
Enter ‘el’ followed by sensor ID to enable the link without module reset
Enter ‘elr’ followed by sensor ID to enable the link with module reset
Enter ‘cm’ to check the module availability
Enter ‘q’ to quit the application

Output
Sensor0_Out0 Frame rate (fps): 29.9989

Output
Sensor0_Out0 Frame rate (fps): 29.9989

Output
Sensor0_Out0 Frame rate (fps): 29.9989

Output
Sensor0_Out0 Frame rate (fps): 30.4989

Output
Sensor0_Out0 Frame rate (fps): 29.9989

Output
Sensor0_Out0 Frame rate (fps): 30.4988

Output
Sensor0_Out0 Frame rate (fps): 29.9989

Output
Sensor0_Out0 Frame rate (fps): 29.9989

Output
Sensor0_Out0 Frame rate (fps): 30.4988

Output
Sensor0_Out0 Frame rate (fps): 29.9989

qOutput
Sensor0_Out0 Frame rate (fps): 29.9989

Output
Sensor0_Out0 Frame rate (fps): 30.4988

q
Output
Sensor0_Out0 Frame rate (fps): 29.9989

Sensor0 Frame captured: 784 Frame drops: 0 Frame discontinuities: 0 Frames authenticated: 0 Frames failed to authenticate: 0 Frames authenticated as Out Of Order: 0
SUCCESS
zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$

SivaRamaKrishnaNV July 1, 2025, 7:55am 14

Dear @deng.shigang ,
I notice the camera platform configuration is added and listed in nvsipl_camera -h . Did you try OX08D10-EXAE-AA1C_R1D_CPHY_x4 as well? Also, could you test with other OX08D10-EXAE-AA1C_R1D_XX_CPHY_x2(x4) config as well? Did you confirm the working DRIVE OS version with omnivison ?

deng.shigang July 2, 2025, 3:31am 15

We tried various methods, including changing cables and ports, but still couldn’t do it. When using the Haowei driver, it is sometimes possible to recognize MAX96712, but after recognition, it takes a while to recognize MAX96712. If using the example program, it can recognize up to MAX96712. So can you help analyze where the problem may lie?

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
Pipeline: 4 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
MAX96722: Revision 5 detected
MAX96712 Link 0: PHY optimization was enabled
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
Pipeline: 4 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
MAX96722: Revision 5 detected
MAX96712 Link 0: PHY optimization was enabled
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
Pipeline: 4 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
MAX96722: Revision 5 detected
MAX96712 Link 0: PHY optimization was enabled
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
Pipeline: 4 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
MAX96722: Revision 5 detected
MAX96712 Link 0: PHY optimization was enabled
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$
zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
nvsipl_camera: ERROR: Master SetPlatformConfig failed. status: 1

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0100 --showfps --autorecovery --disableISP1Output --disableISP2Output
Pipeline: 4 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
MAX96722: Revision 5 detected
MAX96712 Link 0: PHY optimization was enabled
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config “V728S1-120V1-FWC_CPHY_x4” --link-enable-masks “0x0001 0x0000 0x0000 0x0000”
Pipeline: 0 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
Pipeline: 0 ISP Output: 1 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
Pipeline: 0 ISP Output: 2 is using RGBA PACKED FLOAT16 PL SENSOR_RGBA
MAX96712: Revision 5 detected
MAX96712 Link 0: PHY optimization was enabled
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

^[[Azhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config “V728S1-120V1-FWC_CPHY_x4” --link-enable-masks “0x0001 0x0000 0x0000 0x0000”
Pipeline: 0 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
Pipeline: 0 ISP Output: 1 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
Pipeline: 0 ISP Output: 2 is using RGBA PACKED FLOAT16 PL SENSOR_RGBA
MAX96712: Revision 5 detected
MAX96712 Link 0: PHY optimization was enabled
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config “V728S1-120V1-FWC_CPHY_x4” --link-enable-masks “0x0001 0x0000 0x0000 0x0000”
Pipeline: 0 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
Pipeline: 0 ISP Output: 1 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
Pipeline: 0 ISP Output: 2 is using RGBA PACKED FLOAT16 PL SENSOR_RGBA
MAX96712: Revision 5 detected
MAX96712 Link 0: PHY optimization was enabled
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$

deng.shigang July 2, 2025, 3:59am 16

When MAX96712 can be found, more detailed logs will be available

zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$ sudo ./nvsipl_camera --platform-config OX08D10-EXAE-AA1C_CPHY_x2 --link-enable-masks 0x0000 0x0000 0x0000 0x0001 --showfps --autorecovery --disableISP1Output --disableISP2Output -v 4
Platform configuration name: OX08D10-EXAE-AA1C_CPHY_x2
Verbosity level: 4
Raw output: disabled
ISP0 output: enabled
ISP1 output: disabled
ISP2 output: disabled
Enabled FPS logging
Disabled Metadata logging
Enabled automatic recovery
Disabled NvSci
Disabled profiling
Disabled ISP Statistics settings override
Subframe : disabled
Disabled Passive mode
Authentication: controlled by Platform Config
Disabled retrieving/displaying NITO Metadata
nvsipl_camera: Setting up signal handler

nvsipl_camera: Getting platform configuration for OX08D10-EXAE-AA1C_CPHY_x2

nvsipl_camera: Setting link masks

libnvsipl_query.so: CNvMPlatformCfgInfo.cpp : 129: ApplyMask: block:1 enabled
libnvsipl_query.so: CNvMPlatformCfgInfo.cpp : 138: ApplyMask: module:0 enabled
nvsipl_camera: Creating camera master

nvsipl_camera: Setting up master

Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 392: GetInstance: Entering
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 395: GetInstance: Exiting
nvsipl_camera: Creating consumers

Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 807: SetPlatformCfg: Entering DevBlkQueues variant
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 746: SetPlatformCfg: Entering
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 201: SetConfig: Create device block
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 209: SetConfig: Set device block config
Main: CDevBlkDriverLibs.cpp: 135: FindFirstLibPath: Checking “/lib” for drivers
Main: CDevBlkDriverLibs.cpp: 135: FindFirstLibPath: Checking “/lib/nvsipl_drv” for drivers
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820_cust1.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2_sim.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_dms.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623c.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623s.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_max96712tpg.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728_fpdlink.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728c.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_oms.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ds90ub9724_971tpg.so”
Main: CDevBlkDriverLibs.cpp: 147: FindFirstLibPath: Loading library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CDevBlkDriverLibs.cpp: 135: FindFirstLibPath: Checking “/usr/lib” for drivers
Main: CDevBlkDriverLibs.cpp: 135: FindFirstLibPath: Checking “/usr/lib/nvsipl_drv” for drivers
Main: CDevBlkDriverLibs.cpp: 135: FindFirstLibPath: Checking “/usr/local/driveworks/lib” for drivers
Main: CDevBlkDriverLibs.cpp: 135: FindFirstLibPath: Checking “/usr/lib” for drivers
Main: CDevBlkDriverLibs.cpp: 135: FindFirstLibPath: Checking “/usr/lib/nvsipl_drv” for drivers
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820_cust1.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2_sim.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_dms.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623c.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623s.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_max96712tpg.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728_fpdlink.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728c.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_oms.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ds90ub9724_971tpg.so”
Main: CDevBlkDriverLibs.cpp: 225: LoadDriversLibraries: Opening driver library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820_cust1.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2_sim.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_dms.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623c.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623s.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_max96712tpg.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728_fpdlink.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728c.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_oms.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ds90ub9724_971tpg.so”
Main: CNvMDeserializerFactory.cpp: 66: LoadDeserializerDriver: Loading Deserializer driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CDevBlkDriverLibs.cpp: 37: CDevBlkDriverLibs: Driver libraries are already loaded
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820_cust1.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “AR0820C70FOV_24BIT_RGGB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820_cust1.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “VC0820C070R24” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820_cust1.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “VC0820C030R24” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820_cust1.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “OX08D10-EXAE-AA1C” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “OX08D10-EXAE-AA1C_M” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “OX08D10-EXAE-AA1C_F” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “OX08D10-EXAE-AA1C_MF” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “OX08D10-EXAE-AA1C_LC863A” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “OX08D10-EXAE-AA1C_SF816A” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “SIM_V1SIM623S3RU3200NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “SIM_IMX623_30FPS” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V623S2-195V1-SVS” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_dms.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F2O05B1B1DMU1058NB10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_dms.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F2O05B1B1DMU1058NB10_E” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_dms.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V728S1-120V0” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V728S1-120V1-FWC” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V728S1-120V1-SCF” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V728S1-070V1-SCR” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V728S1-030V1-FTC” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V728S1-030V1-RC” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0SIM728S2RU2120NB1” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0SIM728S2RU1070NB1” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0SIM728S2RU2030NB1” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0SIM728S3RU2120NB2” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0SIM728S3RU1070NB2” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0SIM728S3RU2030NB2” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A030BM0A_RCCB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A030BM0A_24BIT_RCCB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A030BM0A_RCCB_BINNING” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A120BM0A_RCCB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A120BM0A_24BIT_RCCB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A120BM0A_RCCB_BINNING” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A030BM0A_RGGB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A030BM0A_24BIT_RGGB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A030BM0A_RGGB_BINNING” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A120BM0A_RGGB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A120BM0A_24BIT_RGGB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A120BM0A_RGGB_BINNING” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A070BM0A_24BIT_RGGB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A030RM0A” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A070RM0A” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A120RM0A” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A120RM0A_SIDE” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F008A120RM0AV2” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “C2SIM623S2RU1195NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623c.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0SIM623S3RU1197NB1” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0SIM623S4RU1197NB2” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623s.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “LI-OV2311-VCSEL-GMSL2-60H” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “LI-OV2311-VCSEL-GMSL2-60H_L” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_max96712tpg.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “MAX96712TPG” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_max96712tpg.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “MAX96712TPG_YUV_8” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_max96712tpg.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623S3RU3200NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623S3RU3200NB20_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623S4RU5195NB3” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623S4RU5195NB3_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V0SIM623S4RU5195NB3” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623S5RU5195NC0” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623S5RU5195NC0_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623S5RU6195NC1” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623S5RU6195NC1_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623SARU6195NC1” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM623SARU6195NC1_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728_fpdlink.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “IMX728_FPDLINK_RGGB” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728_fpdlink.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “C2SIM728S2RU1120NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “C2SIM728S2RU1070HB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “C2SIM728S2RU1070NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “C2SIM728S2RU1030NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728c.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_oms.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “F2O05B1S1DHU1170NB10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_oms.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “SIM_V1SIM728S1RU3120NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “SIM_V1SIM728S1RU3070HB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “SIM_V1SIM728S1RU3030NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “SIM_IMX728_120FOV_30FPS” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “SIM_IMX728_70FOV_30FPS” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “SIM_IMX728_30FOV_30FPS” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0OOX05B1CHU1170NA10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0OOX05B1CHU1170NA10_L” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0OOX05B1CHU1170NA10_LL” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0OOX05B1CHU1170NB10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “R0OOX05B1CHU1170NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S1RU3120NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S1RU3070HB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S1RU3070HB20_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S1RU3030NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU1030NB30” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU3070HB30” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU3070HB30_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU3120NB30” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU3120HB30” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU2030NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU4070HB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU4070HB20_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU4120NB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S2RU4120HB20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU4120NC00” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU4120HC00” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU4070HC00” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU4070HC00_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU2030NC00” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU4120NC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU4120HC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU4070HC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU4070HC10_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU3030NC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728S3RU3030HC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4120NC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4120HC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4070HC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4070HC10_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU3030NC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU3030HC10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4120NC20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4120HC20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4070HC20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4070HC20_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU3030NC20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU3030HC20” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4120NC40” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4120YC40” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4070YC40” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU4070YC40_R” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU3030NC40” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “V1SIM728SARU3030YC40” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ds90ub9724_971tpg.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “DS90UB971TPG” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ds90ub9724_971tpg.so”
Main: CNvMCameraModuleFactory.cpp: 133: LoadDriver: Loading CameraModule driver from library “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “I0OO23111CML1050NB10” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “I0OO23111CML1050NB10_30FPS” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “LI-OV2311-VCSEL-GMSL2-55H” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “LI-OV2311-VCSEL-GMSL2-55H_L” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “I0OO23111CML1050NB10_E” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CNvMCameraModuleFactory.cpp: 179: LoadDriver: Mapping module name “LI-OV2311-VCSEL-GMSL2-55H_E” to module driver “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CNvMMAX96712_96717_OX08D10_R1C.cpp: 59: SetConfigModule: CNvMSensor::SetConfigModule OX08D
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 795: SetPlatformCfg: Exiting
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 835: SetPlatformCfg: Exiting DevBlkQueues variant
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 956: SetPipelineCfg: Entering for pipeline: 4
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/pipelineMgr/spmgr/pipeline/CNvFSensorPipeline.cpp: 59: CapturePreInit: Creating FuSa Capture block
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 38: ThreadCreate: Creating thread:SIPL_CDI_4
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMBufferPool.hpp: 130: Init: Creating buffer pool with 2 buffers
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 137: m_FuncStatic: Thread created
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 122: ThreadSetName: Setting thread name:SIPL_CDI_4
SIPL_CDI_4: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 158: m_Func: Running thread:SIPL_CDI_4
SIPL_CDI_4: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 161: m_Func: Calling ThreadFunc for thread:SIPL_CDI_4
SIPL_CDI_4: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 161: m_Func: Calling ThreadFunc for thread:SIPL_CDI_4
P block
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 1114: SetPipelineCfg: Exiting for pipeline: 4
nvsipl_camera: Creating consumer for output:1 of sensor:4

nvsipl_camera: Profiler initialization for output:1 of sensor:4

nvsipl_camera: Consumer initialization for output:1 of sensor:4

nvsipl_camera: GetPtpDeviceNode() selected /dev/ptp2

nvsipl_camera: Using PTP clock

Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 3344: GetImageAttributes: Entering for pipeline: 4 and output type: 0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 3428: GetImageAttributes: Exiting for pipeline: 4 and output type: 0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 3344: GetImageAttributes: Entering for pipeline: 4 and output type: 1
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 1649: ContainsLowLevelAttributes: NvSciBuf attributes not set.
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 1720: ContainsHighLevelAttributes: NvSciBuf attributes not set.
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 3428: GetImageAttributes: Exiting for pipeline: 4 and output type: 1
Pipeline: 4 ISP Output: 0 is using YUV 420 SEMI-PLANAR UINT8 BL REC_709ER
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 5015: FillNvSciSyncAttrList: Entering for pipeline: 4, output type: 1, and client type: 0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 5072: FillNvSciSyncAttrList: Exiting for pipeline: 4, output type: 1, and client type: 0
nvsipl_camera: Initializing master interface

Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 1400: Init: Entering
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 285: Init: Initializing worker thread for block:0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 38: ThreadCreate: Creating thread:DEVBLK_WORKER_0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 291: Init: Initialized worker thread for block:0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 248: WorkersDoAction: All worker threads starting action:1
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 137: m_FuncStatic: Thread created
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 122: ThreadSetName: Setting thread name:DEVBLK_WORKER_0
DEVBLK_WORKER_0: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 158: m_Func: Running thread:DEVBLK_WORKER_0
DEVBLK_WORKER_0: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 161: m_Func: Calling ThreadFunc for thread:DEVBLK_WORKER_0
DEVBLK_WORKER_0: CNvMMax20087SyncAdapter.cpp: 27: SetConfig: Configure Sync Adapter
DEVBLK_WORKER_0: CNvMMax20087SyncAdapter.cpp: 67: CreatePowerDevice: Create Sync Adapter Driver
DEVBLK_WORKER_0: CNvMMax96712.cpp: 249: DoInit: Check deserializer is present
MAX96722: Revision 5 detected
DEVBLK_WORKER_0: CNvMMax96712.cpp: 256: DoInit: Set deserializer defaults
MAX96712 Link 0: PHY optimization was enabled
DEVBLK_WORKER_0: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 161: m_Func: Calling ThreadFunc for thread:DEVBLK_WORKER_0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 274: WorkersDoAction: All worker threads finished action:1
nvsipl_camera: ERROR: NvSIPLCamera Init failed

nvsipl_camera: ERROR: Master initialization failed. status: 10

nvsipl_camera: Queue timeout

nvsipl_camera: Queue timeout

nvsipl_camera: Queue timeout

Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 5273: Deinit: Entering
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/pipelineMgr/spmgr/pipeline/CNvFSensorPipeline.cpp: 1055: Deinit: Quit the thread
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/pipelineMgr/spmgr/pipeline/blocks/CNvMCDIBlock.cpp: 168: Deinit: Quit the thread
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:SIPL_CDI_4
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 70: ThreadQuit: Waiting for thread:SIPL_CDI_4 to end
SIPL_CDI_4: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 184: m_Func: Exiting thread:SIPL_CDI_4
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 248: WorkersDoAction: All worker threads starting action:4
DEVBLK_WORKER_0: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 161: m_Func: Calling ThreadFunc for thread:DEVBLK_WORKER_0
DEVBLK_WORKER_0: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 184: m_Func: Exiting thread:DEVBLK_WORKER_0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 274: WorkersDoAction: All worker threads finished action:4
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:DEVBLK_WORKER_0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 70: ThreadQuit: Waiting for thread:DEVBLK_WORKER_0 to end
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820_cust1.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox08d10_r1c.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2_sim.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_dms.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728s.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_ar0820.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623c.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623s.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_max96712tpg.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx623vb2.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728_fpdlink.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728c.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05bf_oms.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2_sim.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_ox05b1s.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_imx728vb2.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_ds90ub9724_971tpg.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: CDevBlkDriverLibs.cpp: 74: ~CDevBlkDriverLibs: Closing library: “/lib/nvsipl_drv/libnvsipl_devblk_drv_ov2311_c.so”
Main: CDevBlkDriverLibs.cpp: 76: ~CDevBlkDriverLibs: dlclose
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 248: WorkersDoAction: All worker threads starting action:4
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMDeviceBlockMgr.cpp: 274: WorkersDoAction: All worker threads finished action:4
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:DEVBLK_WORKER_0
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/CNvMCamera.cpp: 5296: Deinit: Exiting
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/pipelineMgr/spmgr/pipeline/blocks/CNvMCDIBlock.cpp: 168: Deinit: Quit the thread
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:SIPL_CDI_4
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:SIPL_CDI_4
Main: /dvs/git/dirty/git-master_modular/camera/fusa/sipl/src/core/utils/CNvMThread.cpp: 60: ThreadQuit: Quitting thread:
zhangzs@tegra-ubuntu:/opt/nvidia/drive-linux/samples/nvmedia/nvsipl/test/camera$

SivaRamaKrishnaNV July 2, 2025, 5:31am 17

Do you have only one devkit? If not, could you try with other devkit as well?
Did you ever try with other camera modules on this target?
Do you have any other camera modules(from other vendor) to check if issue with port? AFAIU, issue does not look like with target.

Could you please share the syslog output generated when running nvsipl_camera. You may clear the previous output from syslog.

deng.shigang July 2, 2025, 6:37am 18

We have tried both Orin development kits and the results are the same.
At present, we only have OX08D10 modules.
The output of syslog is as follows

txt.log (29.8 KB)

deng.shigang July 3, 2025, 1:09am 19

@SivaRamaKrishnaNV Is there any update? Our project is quite urgent, please

SivaRamaKrishnaNV July 3, 2025, 4:50am 20

Dear @deng.shigang ,
Can you check the private message and share the asked info to take it forward.

1437514418 July 3, 2025, 8:47am 21

@SivaRamaKrishnaNV Due to Deng Shigang’s account being unable to log in, we can use this 1437514418@qqcom Will the account continue to communicate?

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