Hello ,
I want to upgrade the jetpack on my xavier from 4.3 to 4.4. I could successfully flash the xavier with jetpack 4.4 using sdk manager. But ,the xavier does not boot up successfully. I’m attaching the uart output. It complains about an i2c timeout.Pointers on how to debug this would be useful. Let me know if you need more info. Thanks.
[ 83.5452c 31c0000.i2c: I2C_CNFG - 0x22c00
[ 93.785200] tegra-i2c 31c0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x10001
[ 93.785203] tegra-i2c 31c0000.i2c: I2C_FIFO_CONTROL - 0x0
[ 93.785207] tegra-i2c 31c0000.i2c: I2C_FIFO_STATUS - 0x800080
[ 93.785210] tegra-i2c 31c0000.i2c: I2C_MST_FIFO_CONTROL - 0x70
[ 93.785213] tegra-i2c 31c0000.i2c: I2C_MST_FIFO_STATUS - 0x7c0000
[ 93.785216] tegra-i2c 31c0000.i2c: I2C_MST_PACKET_TRANSFER_CNT - 0x0
[ 93.785219] tegra-i2c 31c0000.i2c: I2C_INT_[ 104.025174] tegra-i2c 31c0000.i2c: rx dma timeout txlen:28 rxlen:128
[ 104.025339] tegra-i2c 31c0000.i2c: --- register dump for debugging ----
[ 104.025472] tegra-i2c 31c0000.i2c: I2C_CNFG - 0x22c00
[ 104.025567] tegra-i2c 31c0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x10001
[ 104.025678] tegra-i2c 31c0000.i2c: I2C_FIFO_CONTROL - 0x0
[ 104.025769] tegra-i2c 31c0000.i2c: I2C_FIFO_STATUS - 0x800080
[ 104.025877] tegra-i2c 31c0000.i2c: I2C_MST_FIFO_CONTROL - 0x70
[ 104.025979] tegra-i2c 31c0000.i2c: I2C_MST_FIFO_STATUS - 0x7c0000
[ 104.026084] tegra-i2c 31c0000.i2c: I2C_MST_PACKET_TRANSFER_CNT - 0x0
[ 104.026208] tegra-i2c 31c0000.i2c: I2C_INT_MASK - 0x6c
[ 104.026299] tegra-i2c 31c0000.i2c: I2C_INT_STATUS - 0x2
[ 104.026394] tegra-i2c 31c0000.i2c: i2c transfer timed out addr: 0x50
[ 114.265175] tegra-i2c 31c0000.i2c: rx dma timeout txlen:28 rxlen:128
[ 114.265336] tegra-i2c 31c0000.i2c: --- register dump for debugging ----
[ 114.265452] tegra-i2c 31c0000.i2c: I2C_CNFG - 0x22c00
[ 114.265541] tegra-i2c 31c0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x10001
[ 114.265652] tegra-i2c 31c0000.i2c: I2C_FIFO_CONTROL - 0x0
[ 114.265743] tegra-i2c 31c0000.i2c: I2C_FIFO_STATUS - 0x800080
[ 114.265842] tegra-i2c 31c0000.i2c: I2C_MST_FIFO_CONTROL - 0x70
[ 114.265940] tegra-i2c 31c0000.i2c: I2C_MST_FIFO_STATUS - 0x7c0000
[ 114.266042] tegra-i2c 31c0000.i2c: I2C_MST_PACKET_TRANSFER_CNT - 0x0
[ 114.266149] tegra-i2c 31c0000.i2c: I2C_INT_MASK - 0x6c
[ 114.266234] tegra-i2c 31c0000.i2c: I2C_INT_STATUS - 0x2
[ 114.266333] tegra-i2c 31c0000.i2c: i2c transfer timed out addr: 0x50
[ 124.505170] tegra-i2c 31c0000.i2c: rx dma timeout txlen:28 rxlen:128
[ 124.505345] tegra-i2c 31c0000.i2c: --- register dump for debugging ----
[ 124.505474] tegra-i2c 31c0000.i2c: I2C_CNFG - 0x22c00
[ 124.505581] tegra-i2c 31c0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x10001
[ 124.505697] tegra-i2c 31c0000.i2c: I2C_FIFO_CONTROL - 0x0
[ 124.505789] tegra-i2c 31c0000.i2c: I2C_FIFO_STATUS - 0x800080
[ 124.505884] tegra-i2c 31c0000.i2c: I2C_MST_FIFO_CONTROL - 0x70
[ 124.505997] tegra-i2c 31c0000.i2c: I2C_MST_FIFO_STATUS - 0x7c0000
[ 124.506104] tegra-i2c 31c0000.i2c: I2C_MST_PACKET_TRANSFER_CNT - 0x0
[ 124.506211] tegra-i2c 31c0000.i2c: I2C_INT_MASK - 0x6c
[ 124.506298] tegra-i2c 31c0000.i2c: I2C_INT_STATUS - 0x2
[ 124.506407] tegra-i2c 31c0000.i2c: i2c transfer timed out addr: 0x50
[ 124.507228] tegradc 15200000.nvdisplay: hdmi: edid read failed
��WARNING: pll_d3 has no dyn ramp
��[ 134.745169] tegra-i2c 31c0000.i2c: rx dma timeout txlen:28 rxlen:128
[ 134.745177] tegra-i2c 31c0000.i2c: --- register dump for debugging ----
[ 134.745186] tegra-i2c 31c0000.i2c: I2C_CNFG - 0x22c00
[ 134.745190] tegra-i2c 31c0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x10001
[ 134.745195] tegra-i2c 31c0000.i2c: I2C_FIFO_CONTROL - 0x0
[ 134.745199] tegra-i2c 31c0000.i2c: I2C_FIFO_STATUS - 0x800080
[ 134.745203] tegra-i2c 31c0000.i2c: I2C_MST_FIFO_CONTROL - 0x70
[ 134.745206] tegra��WARNING: pll_d3 has no dyn ramp