Nano Input Pin States

Hi I had a few follow-up questions about the Pin States on Power-up of the Nano:

  1. Are there any specific pins that need to be floated during powerup, is there somewhere in the design guide I can reference, we are seeing issues with reliable power-up from board to board and what to confirm we are correctly setting the states of the pins?
    2.Should FORCE_RECOVERY* be connected as open-drain and floating during boot-up?
  2. We see that SHUTDOWN_REQ* goes to 5V during power up is this expected behavior?
  3. Is there any concern with providing 3.3V to PMIC_BBAT prior to booting up the Nano or enabling the VDD_IN 5V rail?

Specifically regarding SHUTDOWN_REQ* when we externally power off the Nano can the carrier board assert SHUTDOWN_REQ*?
Thank you,

Hi, are there any updates on these questions, I would appreciate feedback.
Thank you

For default pins status, you can refer to the pinmux sheet, also you can refer to the checklist in OEM Design Guide to check your custom design, most unused pins can be float. Both pinmux and DG are in DLC.

Force_recovery* should be float or high during boot-up so as not to enter recovery mode.

Shutdonw_req* should be high during power-up, it is used by the module only to request the carrier board to shut down.

PMIC_BBAT can be always ON.

Thanks for the reply,
I have a few follow-up questions about the comment you made on the Shutdown_REQ*:
“Shutdonw_req* should be high during power-up, it is used by the module only to request the carrier board to shut down”

  1. Do you mean that it is required/recommended to have a buffer to separate the forced power off logic from the SHUTDOWN_REQ* signal of the module as shown in your dev-kit schematic? In our custom design we have that buffer bypassed, such that when we force shutdown it directly pulls that the SHUTDOWN_REQ* signal low.
  2. I see that on the dev-kit the button press line is tied to this logic and also to the sleep/wake pin on the Module. Is it necessary to first assert the sleep/wake line prior to a force shutdown, and are there any timing requirements for that sequence?
  3. Is there a reason that you have a 10 second delay on a force shutdown, or is that merely to prevent accidental shutdown via a button press?

Thank you,

Suggest to totally follow the page of Power ON/OFF Logic in reference schematic including the buffer.

No need to handle sleep/wake line for a force shutdown by FORCE_OFF.

The 10s circuit is for the function of long-press shutdown which is implemented through POWER_EN. Better to keep it as a hardware force shutdown.

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