Please provide the following info (check/uncheck the boxes after creating this topic): Software Version
DRIVE OS Linux 5.2.6
DRIVE OS Linux 5.2.6 and DriveWorks 4.0
DRIVE OS Linux 5.2.0
DRIVE OS Linux 5.2.0 and DriveWorks 3.5
NVIDIA DRIVE™ Software 10.0 (Linux)
NVIDIA DRIVE™ Software 9.0 (Linux)
other DRIVE OS version
other
with older DRIVE OS 5.1.15.0-20186720 I was able to connect two monitors to the HDMI inputs 1 and 2 and to stream two different camera inputs to the screens with the -d 0 and -d 1 command line switches. This is not possible anymore with the 5.2.6.0-27062047.
first terminal:
Port B camera input as Output on first screen:
~/drive-t186ref-linux/samples/nvmedia/nvsipl/test/camera/nvsipl_camera -c “F008A120RM0A_CPHY_x4” -m “0x0000 0x0001 0x0000 0x0000” --disableISP1Output --showfps -a -w 1 -d 0
second terminal:
Port D camera input as Output on second screen:
~/drive-t186ref-linux/samples/nvmedia/nvsipl/test/camera/nvsipl_camera -c “F008A120RM0A_CPHY_x4” -m “0x0000 0x0000 0x0000 0x0010” --disableISP1Output --showfps -a -w 1 -d 1
with
~/drive-t186ref-linux/samples/nvmedia/nvsipl/test/camera/nvsipl_camera -h
nvidia@tegra-ubuntu:~$ ~/drive-t186ref-linux/samples/nvmedia/nvsipl/test/camera/nvsipl_camera -h
Usage:
-h or --help :Prints this help
-c or --platform-config 'name' :Platform configuration. Supported values
IMX390RGGBMP_200FOV_RGGB_CPHY_x2 :IMX390RGGBMP_200FOV RGGB module in 2 lane CPHY mode
IMX390RGGBMP_200FOV_RGGB_CPHY_x2_TPG:IMX390RGGBMP_200FOV RGGB module in 2 lane CPHY, TPG mode
IMX390RGGBMP_200FOV_RGGB_CPHY_x4 :IMX390RGGBMP_200FOV RGGB module in 4 lane CPHY mode
IMX390RGGBMP_200FOV_RGGB_CPHY_x4_TPG:IMX390RGGBMP_200FOV RGGB module in 4 lane CPHY, TPG mode
IMX390RGGBE3_200FOV_RGGB_CPHY_x2 :IMX390RGGBE3_200FOV RGGB module in 2 lane CPHY mode
IMX390RGGBE3_200FOV_RGGB_CPHY_x2_TPG:IMX390RGGBE3_200FOV RGGB module in 2 lane CPHY, TPG mode
IMX390RGGBE3_200FOV_RGGB_CPHY_x4 :IMX390RGGBE3_200FOV RGGB module in 4 lane CPHY mode
IMX390RGGBE3_200FOV_RGGB_CPHY_x4_TPG:IMX390RGGBE3_200FOV RGGB module in 4 lane CPHY, TPG mode
IMX390RGGBE5_200FOV_RGGB_CPHY_x2 :IMX390RGGBE5_200FOV RGGB module in 2 lane CPHY mode
IMX390RGGBE5_200FOV_RGGB_CPHY_x2_TPG:IMX390RGGBE5_200FOV RGGB module in 2 lane CPHY, TPG mode
IMX390RGGBE5_200FOV_RGGB_CPHY_x4 :IMX390RGGBE5_200FOV RGGB module in 4 lane CPHY mode
IMX390RGGBE5_200FOV_RGGB_CPHY_x4_TPG:IMX390RGGBE5_200FOV RGGB module in 4 lane CPHY, TPG mode
MAX96712_RAW12_TPG_DPHY_x2 :MAX96712 RAW12 TPG in 2 lane DPHY mode
MAX96712_RAW12_TPG_DPHY_x4 :MAX96712 RAW12 TPG in 4 lane DPHY mode
MAX96712_RAW12_TPG_CPHY_x2 :MAX96712 RAW12 TPG in 2 lane CPHY mode
MAX96712_RAW12_TPG_CPHY_x4 :MAX96712 RAW12 TPG in 4 lane CPHY mode
MAX96712_RGB_TPG_DPHY_x2 :MAX96712 RGB TPG in 2 lane DPHY mode
MAX96712_RGB_TPG_DPHY_x4 :MAX96712 RGB TPG in 4 lane DPHY mode
MAX96712_RGB_TPG_CPHY_x2 :MAX96712 RGB TPG in 2 lane CPHY mode
MAX96712_RGB_TPG_CPHY_x4 :MAX96712 RGB TPG in 4 lane CPHY mode
MAX96712_YUV_8_TPG_DPHY_x2 :MAX96712 YUV 8-bit TPG in 2 lane DPHY mode
MAX96712_YUV_8_TPG_DPHY_x4 :MAX96712 YUV 8-bit TPG in 4 lane DPHY mode
MAX96712_YUV_8_TPG_CPHY_x2 :MAX96712 YUV 8-bit TPG in 2 lane CPHY mode
MAX96712_YUV_8_TPG_CPHY_x4 :MAX96712 YUV 8-bit TPG in 4 lane CPHY mode
MAX96712_TPG_USECASE1_CPHY_x4 :MAX96712 TPG USECASE1 in 4 lane CPHY mode
MAX96712_TPG_USECASE2_CPHY_x4 :MAX96712 TPG USECASE2 in 4 lane CPHY mode
MAX96712_2880x1860_YUV_8_TPG_DPHY_x2:MAX96712 YUV 8-bit TPG in 2 lane DPHY mode
MAX96712_2880x1860_YUV_8_TPG_DPHY_x4:MAX96712 YUV 8-bit TPG in 4 lane DPHY mode
MAX96712_2880x1860_YUV_8_TPG_CPHY_x2:MAX96712 YUV 8-bit TPG in 2 lane CPHY mode
MAX96712_2880x1860_YUV_8_TPG_CPHY_x4:MAX96712 YUV 8-bit TPG in 4 lane CPHY mode
CONSTELLATION_T_2MP_DPHY_x4 :Constellation 1920x1208 capture in 4 lane DPHY mode
CONSTELLATION_T_8MP_DPHY_x4 :Constellation 3848x2168 capture in 4 lane DPHY mode
CONSTELLATION_T_2MP_TPG_DPHY_x4 :Constellation 1920x1236 capture in 4 lane DPHY mode
CONSTELLATION_T_YUV8_2MP_DPHY_x4 :Constellation 1920x1208 capture in 4 lane DPHY mode
SF3325_DPHY_x2 :SF3325 module in 2 lane DPHY mode
SF3325_DPHY_x2_TPG :SF3325 module in 2 lane DPHY, TPG mode
SF3325_CPHY_x2 :SF3325 module in 2 lane CPHY mode
SF3325_CPHY_x2_TPG :SF3325 module in 2 lane CPHY, TPG mode
SF3325_DPHY_x4 :SF3325 module in 4 lane DPHY mode
SF3325_DPHY_x4_TPG :SF3325 module in 4 lane DPHY, TPG mode
SF3325_CPHY_x4 :SF3325 module in 4 lane CPHY mode
SF3325_CPHY_x4_TPG :SF3325 module in 4 lane CPHY, TPG mode
SF3324_DPHY_x2 :SF3324 module in 2 lane DPHY mode
SF3324_DPHY_x2_TPG :SF3324 module in 2 lane DPHY, TPG mode
SF3324_CPHY_x2 :SF3324 module in 2 lane CPHY mode
SF3324_CPHY_x2_TPG :SF3324 module in 2 lane CPHY, TPG mode
SF3324_DPHY_x4 :SF3324 module in 4 lane DPHY mode
SF3324_DPHY_x4_TPG :SF3324 module in 4 lane DPHY, TPG mode
SF3324_CPHY_x4 :SF3324 module in 4 lane CPHY mode
SF3324_CPHY_x4_TPG :SF3324 module in 4 lane CPHY, TPG mode
F008A070RM0A_CPHY_x2 :F008A070RM0A 24BIT RGGB module in 2 lane CPHY mode
F008A070RM0A_CPHY_x2_TPG :F008A070RM0A 24BIT RGGB module in 2 lane CPHY, TPG mode
F008A070RM0A_CPHY_x4 :F008A070RM0A 24BIT RGGB module in 4 lane CPHY mode
F008A070RM0A_CPHY_x4_TPG :F008A070RM0A 24BIT RGGB module in 4 lane CPHY, TPG mode
F008A030RM0A_CPHY_x2 :F008A030RM0A 24BIT RGGB module in 2 lane CPHY mode
F008A030RM0A_CPHY_x2_TPG :F008A030RM0A 24BIT RGGB module in 2 lane CPHY, TPG mode
F008A030RM0A_CPHY_x4 :F008A030RM0A 24BIT RGGB module in 4 lane CPHY mode
F008A030RM0A_CPHY_x4_TPG :F008A030RM0A 24BIT RGGB module in 4 lane CPHY, TPG mode
F008A120RM0A_SIDE_CPHY_x2 :F008A120RM0A 24BIT RGGB module in 2 lane CPHY mode
F008A120RM0A_SIDE_CPHY_x2_TPG :F008A120RM0A 24BIT RGGB module in 2 lane CPHY, TPG mode
F008A120RM0A_SIDE_CPHY_x4 :F008A120RM0A 24BIT RGGB module in 4 lane CPHY mode
F008A120RM0A_SIDE_CPHY_x4_TPG :F008A120RM0A 24BIT RGGB module in 4 lane CPHY, TPG mode
F008A120RM0A_CPHY_x2 :F008A120RM0A 24BIT RGGB module in 2 lane CPHY mode
F008A120RM0A_CPHY_x2_TPG :F008A120RM0A 24BIT RGGB module in 2 lane CPHY, TPG mode
F008A120RM0A_CPHY_x4 :F008A120RM0A 24BIT RGGB module in 4 lane CPHY mode
F008A120RM0A_CPHY_x4_TPG :F008A120RM0A 24BIT RGGB module in 4 lane CPHY, TPG mode
AR0144P_DPHY_x2 :AR0144P module in 2 lane DPHY mode
AR0144P_DPHY_x2_TPG :AR0144P module in 2 lane DPHY, TPG mode
AR0144P_DPHY_x4 :AR0144P module in 4 lane DPHY mode
AR0144P_DPHY_x4_TPG :AR0144P module in 4 lane DPHY, TPG mode
IMX390_C_3461_F200_RGGB_DPHY_x2 :IMX390_C_3461 RGGB module in 2 lane DPHY mode
IMX390_C_3461_F200_RGGB_DPHY_x2_TPG:IMX390_C_3461 RGGB module in 4 lane DPHY, TPG mode
IMX390_C_3461_F200_RGGB_DPHY_x4 :IMX390_C_3461 RGGB module in 4 lane DPHY mode
IMX390_C_3461_F200_RGGB_DPHY_x4_TPG:IMX390_C_3461 RGGB module in 4 lane DPHY, TPG mode
IMX390_C_3461_F200_RGGB_CPHY_x4 :IMX390_C_3461 RGGB module in 4 lane CPHY mode
IMX390_C_3461_F200_RGGB_CPHY_x2 :IMX390_C_3461 RGGB module in 2 lane CPHY mode
IMX390_C_3461_F200_RGGB_CPHY_x2_TPG:IMX390_C_3461 RGGB module in 4 lane CPHY, TPG mode
IMX390_C_3461_F200_RGGB_CPHY_x4_TPG:IMX390_C_3461 RGGB module in 4 lane CPHY, TPG mode
OV2311_C_3461_CPHY_x2 :OV2311(C) module in 2 lane CPHY mode
OV2311_C_3461_CPHY_x2_TPG :OV2311(C) module in 2 lane CPHY, TPG mode
CONSTELLATION_2MP_DPHY_x2 :Constellation 1920x1208 capture in 2 lane DPHY mode
CONSTELLATION_8MP_CPHY_x4 :Constellation 3848x2168 capture in 4 lane CPHY mode
CONSTELLATION_2MP_TPG_DPHY_x2 :Constellation 1920x1208 tpg capture with in 2 lane DPHY mode
VC0820C120R24_24BIT_RGGB_CPHY_x2 :AR0820 120FOV 24BIT RGGB module in 2 lane CPHY mode
VC0820C120R24_24BIT_RGGB_CPHY_x2_TPG:AR0820 120FOV 24BIT RGGB module in 2 lane CPHY, TPG mode
AR0820C120FOV_24BIT_RGGB_CPHY_x2 :AR0820C120FOV_24BIT(B0) RGGB module in 2 lane CPHY mode
AR0820C120FOV_24BIT_RGGB_CPHY_x2_TPG:AR0820C120FOV_24BIT(B0) RGGB module in 2 lane CPHY, TPG mode
AR0820C70FOV_24BIT_RGGB_CPHY_x2 :AR0820C70FOV_24BIT(B0) RGGB module in 2 lane CPHY mode
AR0820C70FOV_24BIT_RGGB_CPHY_x2_TPG:AR0820C70FOV_24BIT(B0) RGGB module in 2 lane CPHY, TPG mode
VC0820C070R24_CPHY_x2 :AR0820 70FOV 24BIT RGGB module in 2 lane CPHY mode
VC0820C070R24_CPHY_x2_TPG :AR0820 70FOV 24BIT RGGB module in 2 lane CPHY, TPG mode
--link-enable-masks 'masks' :Enable masks for links on each deserializer connected to CSI
:masks is a list of masks for each deserializer.
:Eg: '0x0000 0x1101 0x0000 0x0000' disables all but links 0, 2 and 3 on CSI-CD intrface
-r or --runfor <seconds> :Exit application after n seconds
-v or --verbosity <level> :Set verbosity
:Supported values (default: 1)
: 0 (None)
: 1 (Errors)
: 2 (Warnings and above)
: 3 (Infos and above)
: 4 (Debug and above)
-t or --test-config-file <file> :Set custom platform config json file
-l or --list-configs :List configs from file specified via -t or --test-config-file
--enableRawOutput :Enable the Raw output
--disableISP0Output :Disable the ISP0 output
--disableISP1Output :Disable the ISP1 output
--showfps :Show FPS (frames per second) every 2 seconds
--showmetadata :Show Metadata when RAW output is enabled
--plugin <type> :Auto Control Plugin. Supported types (default: If nito available 0 else 1)
: 0 Nvidia AE/AWB Plugin
: 1 Custom Plugin
--autorecovery :Recover deserializer link failure automatically
--nvsci :Use NvSci for communication and synchronization
--profile :Enable profiling of capture KPIs
--initProfile :Enable profiling of the initialization sequence
--nito <folder> :Path to folder containing NITO files
--icrop 'y+h' :Specifies the cropping at the input in the format 'y+h'
--showEEPROM :Show EEPROM data
--ignoreError :Ignore the fatal error
-d or --disp-id <ID> :Display ID.
Number of available displays: 1
-w or --disp-win-id <ID> :Display window ID. Supported values 0 to 2
-z or --disp-win-depth <val> :Display window depth. Supported values 0 to 255
-p or --disp-win-pos 'rect' :Display position, where rect is x0, y0, width, height
-f or --filedump-prefix 'str' :Dump RAW file with filename prefix 'str' when RAW output is enabled.
-i or --input-raw-files <file1[,file2]...> :Set input RAW files for simulator mode testing.
:Use comma separator for multiple files.
--enableSecondary :Enable secondary mode
--autoLED :Enable automatic LED control, specifically for AR0234
--skipFrames <val> :Number of frames to skip before writing to file
--writeFrames <val> :Number of frames to write to file
--showNitoMetadata :Get and display NITO Metadata (ID, dataHash, schemaHash) from NITO file(s) to console.
--numParameterSetsInNITO <val> :Number of parameter sets in NITO file. Defaults to 10, must be >=1. Use if expecting >10 parameter sets in NITO file(s).
nvidia@tegra-ubuntu:~$
The code snippet is in ~/nvidia/nvidia_sdk/DRIVE_OS_5.2.6_SDK_*/DRIVEOS/drive-t186ref-linux/samplesnvmedia/nvsipl/test/camera/CCmdLineParser.hpp.
But I don’t think it matters.
Did you see any error messages while running on DRIVE OS 5.2.6?
Yes, that’s the verified official downgrade path.
DRIVE OS 5.1.15 isn’t a developer site release so if you have any problems with 5.1.15, you will have to get support via your other channel.