Orin AGX adaptation to Xavier-based custom PCB (PCIe C4, C7)

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
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Hello Nvidia forums,
we are adapting our Xavier-based PCB for Orin usage and there is a slight problem with pins that were in Xavier AGX designated as C4.

One of the PCIE interfaces (Mini-PCIE) is connected to C4, and was working in the Xavier AGX without any problems. However, there seems to be a difference in the pinout between Xavier and Orin. This problem is further exacerbated by the fact that the C7 (lanes 0,1,2,3 and its appropriate clkreq+rst) is already in use for another interface (M2 drive slot). In the below table you can see pins used for the Mini-PCIE, which refuses to show up in the lspci listing (did I compile this data correctly, or is my line of thinking wrong?):

pin # xavier name orin name comment
A14 PEX4_RX0N PEX7_RX6N mismatch
A15 PEX4_RX0P PEX7_RX6P mismatch
C14 PEX4_RX1N PEX7_RX7N mismatch
C15 PEX4_RX1P PEX7_RX7P mismatch
J15 PEX4_TX0N PEX7_TX6N mismatch
J14 PEX4_TX0P PEX7_TX6P mismatch
G14 PEX4_TX1N PEX7_TX7N mismatch
G15 PEX4_TX1P PEX7_TX7P mismatch
E22 PEX_CLK_OUT_4_N PEX_CLK_OUT_4_N
E23 PEX_CLK_OUT_4_P PEX_CLK_OUT_4_P
G8 PE4_CLKREQ_L PE4_CLKREQ_L
J9 PE4_RST_L PE4_RST_L

The above table contains pin # and the pin names as from the Pinmux Spreadsheet.

Below is my config for the C4 and C7. C4 is wired to the problematic interface.

// PCIE C4 CONFIG ===========================================================


                        pex_l4_clkreq_n_pl0 {
                                nvidia,pins = "pex_l4_clkreq_n_pl0";
                                nvidia,function = "pe4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

                        pex_l4_rst_n_pl1 {
                                nvidia,pins = "pex_l4_rst_n_pl1";
                                nvidia,function = "pe4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };


// PCIE C7 CONFIG ================


                        pex_l7_clkreq_n_pag0 {
                                nvidia,pins = "pex_l7_clkreq_n_pag0";
                                nvidia,function = "pe7";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

                        pex_l7_rst_n_pag1 {
                                  nvidia,pins = "pex_l7_rst_n_pag1";
                                  nvidia,function = "pe7";
                                  nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                  nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                  nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                  nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                                  nvidia,lpdr = <TEGRA_PIN_DISABLE>;

                        };

My device-tree config, I tried to somehow force the mismatched pins into the pcie@14160000 node:


	// Mini-PCIE, C4 ROOT PORT x2
	pcie@14160000 {
		status = "okay";
		// phys = <&p2u_hsio_4>, <&p2u_hsio_5>;//, <&p2u_hsio_6>, <&p2u_hsio_7>;

		phys = <&p2u_gbe_6>, <&p2u_gbe_7>; // Orin: C7 vs C4??
		phy-names = "p2u-0", "p2u-1";//, "p2u-2", "p2u-3";
		num-lanes = <2>;
		nvidia,disable-power-down;
    	// max-link-speed = <1>;     // Optional
	};
		
	// M.2, C7 ROOT PORT x4
    pcie@141e0000 {
		status = "okay";
		num-lanes = <4>;
		phys = <&p2u_gbe_0>, <&p2u_gbe_1>, <&p2u_gbe_2>, <&p2u_gbe_3>;//, <&p2u_gbe_4>, <&p2u_gbe_5>, <&p2u_gbe_6>, <&p2u_gbe_7>;
		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";//, "p2u-4", "p2u-5", "p2u-6", "p2u-7";
    };

As you can see C7 lanes (0,1,2,3) are already taken by pcie@141e0000, and AFAIK I cannot just assign phys = <&p2u_gbe_6>, <&p2u_gbe_7>; to pcie@14160000.

My lspci output:

nvidia@orin:~$ lspci
0000:00:00.0 PCI bridge: NVIDIA Corporation Device 229c (rev a1)
0001:00:00.0 PCI bridge: NVIDIA Corporation Device 229e (rev a1)
0004:00:00.0 PCI bridge: NVIDIA Corporation Device 229c (rev a1)
0007:00:00.0 PCI bridge: NVIDIA Corporation Device 229a (rev a1)
0007:01:00.0 Non-Volatile memory controller: ADATA Technology Co., Ltd. XPG SX8200 Pro PCIe Gen3x4 M.2 2280 Solid State Drive (rev 03)

Is my line of reasoning correct, is there a pin mismatch?

If yes, is there a way to re-use idle C7 lanes in another interface?

Best regards,
Jerry

4

On Jetson AGX Orin, there is no PCIe controller mapped specifically for 2-lane functionality on the pins you re-used from Jetson AGX Xavier (marked in red). In the clip below from Table 5 of Jetson AGX Orin Series and Jetson AGX Xavier Series Interface Migration, Xavier supports a x2 PCIe on controller 4 but Orin does not have a controller mapped specifically for a x2 interface on those same pins. On Orin, those pins map to lanes 6 and 7 of a PCIe x8 on controller 7, but C7 can only support a x2 interface on the lanes marked in blue. Orin’s PCIe controller cannot remap a x2 interface to the same pins as Xavier’s C4 x2.

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