Orin Nano Power Up Sequence

In figure 6-3 in the Orin Nano Design Guide, there is a delay of 400 ms between VDD_IN and POWER_EN but I see no other mention of this anywhere on the document. Is this needed? Why?

The 400ms delay will be removed in future new release.

Great, so we do not have to design it in?

Why is it there?

Because of different PMIC inside.

When can we expect this change to be made? Do we need to support both delays?

It is for all exist Orin NX/Nano, 400ms is for Jetson nano only.

Ok, should we put a request in to update all of the documentation since it does not ever apply to this series?

As said, the related docs will be updated.

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