Tegra K1 PCIe Interface

Hi,
I am trying to use following features.Use case 3 in the table 40 in the page 42 of 113.

  1. 4x PCIe : PEX_TX/RX[4:1]
  2. GIGE LAN : USB3_TX/RX0
  3. SATA:SATA

But there are conflicting statements made in the design guideline of the Tegra K1.
I would like to know the controllers and their reference clocks associated with each PCIe lane.
Thank you

PLLE is the clock for PCIe, you can get details in technical reference manual.
https://developer.nvidia.com/tegra-k1-technical-reference-manual