TX2 PCIe SI Simulations in Hyperlynx

We are designing product based around the TX2 module. I was surprised to find that there wasn’t an IBIS model provided for the module itself. The only IBIS module I see is parker_18mx18m.ibs for the IC itself. It does look like S-paramters are provided for most of the high-speed interfaces on the module, but not the PCIe. I was also surprised to see the the PCIe model in the parker_18x18mm.ibs module refers to an external spice model that was not included in the zip file I downloaded. There doesn’t seem to be an RX model for the PCIe. Can you tell me how Nvidia recommends simulating the signal integrity of the PCIE interface of the TX2 Module based on what is provided?

External Model
Corner Typ x1_pcie_tx_spice.sp pcie_tx_gen2_typ_3d5dB

Thanks,
RADENG

In addition to the PCIe interface, I also don’t see anything provided that would enable simulation of the 1Gb Ethernet Interface (GBE_MDI*). Can you also provide guidance or a model for this interface?
Thanks!

Hi, there will be a updated package if available, please wait for its release.

Trumany, when do you expect the package to be released? We are beginning our simulation process now. Is is possible to get a preliminary release?

No ETA by now, please wait for the release.

Trumany,

We are in layout now and simulating the design? Is there any way to get us some sort of model to be able to simulate the TX2 interface? We really don’t have the ability to wait. I can not believe there isn’t some ability to simulate the TX2 PCIe interface. There must be something Nvidia can provide.
Thanks

Please check the new update package here: http://developer.nvidia.com/embedded/dlc/jetson-tx2-sparameter-files

Are you implying this is where I should check in the futrue or that the new package is available now? The parker IBIS model in the link still contains a link to a spice file, x1_dp_tx_spice.sp, that is not included in the zip file. Also, there doesn’t seem to be any PCIe related S-Parameters and there is no PCIe RX simulation model, only TX.

[External Model]
Language SPICE
|
| Corner corner_name file_name circuit_name
Corner Typ x1_dp_tx_spice.sp dp_typ_0db
Corner Min x1_dp_tx_spice.sp dp_typ_0db
Corner Max x1_dp_tx_spice.sp dp_typ_0db

Are you talking about the latest package (ver 6/13) ? The x1_dp_tx_spice.sp and PCIe RX files are already in it.