Unable to get SPI Master and Slave devices on Jetson GPIO

andrew.taylor · April 8, 2025, 9:58am

Hi there! 😄

I’m currently trying to get two SPI devices set up on my Jetson AGX Orin on its GPIO. I’d like one SPI device to act as a master device and another to act as a Slave. Unfortunately I’m having some trouble with setting this up. ⚠️

⛓️‍💥 What is the problem?

I currently have two SPI devices set up on my Jetson, spi@3210000 (bus 0) and spi@3230000 (bus 2) in the device tree. I’ve performed a loopback test using the spidev_test.c library for each of these buses. The compiled binary file for the spidev_test was taken from this forum post. Below are the results from my testing with both buses as Masters.

Bus 0 - Passed successfully with data being transmitted and received
Bus 2 - Passed only when transmitting data. Cannot receive data.

Below is the wiring configuration for the tests:

Bus 0 - Pins 19 and 21 connected
Bus 2 - Pins 37 and 22 connected

🧪 My hypothesis

I’ve been following this post to try to configure the SPI devices. I’ve managed to follow it completely except one step, activating spi3 using the jetson-io.py script. When I run the script and try to manually configure the 40-pin header I’m only presented with the option for spi1 not spi3 .

I think bus 2 is working correctly, it’s just not able to read from the GPIO pins because it’s not configured. I’m hoping that if I can activate the spi3 function in the jetson-io.py things should fall into place.

🛠️ What have I tried?

Following the forum post here
- Validated whether the buses are working as expected
- Verified my pin connections
- Used devmem2 to edit the pinmux settings for spi1 and spi3 based on the memory addresses seen there.
- Made changes to the device tree to configure bus 2 as a Slave and rebooted the Jetson with the new dtb enabled.
Read through the Platform and Adaptation documentation
Read through the MB1 Configuration Changes documentation
Followed the instructions in the Configuring the Jetson Expansion Headers documentation
Read through this forum post about alternative functions on GPIO
Attempted to add a hardware overlay for the spi3 pins 37, 22, 13, 18, 16 following the instructions here
- This failed to work with Invalid function spi3! , I also tried this with spi2 but this also failed to work with the same error.
Attempted to follow the instructions in the elinux loopback test guide however I ran into the following issues:
- I couldn’t find a file that was closely similar in /boot to that mentioned in step 2-2-2-2 (Dissemble the dtb to dts).
- I dissembled and attempted to edit the DTB already in use for booting as defined in /boot/extlinux/extlinux.conf did not contain the gpio-input field for me to edit as per step 2-2-2-3 (Modify the gpio-input field).

You may have noticed that I’ve not mentioned changing the Pinmux spreadsheet here and reflashing my device. I’d like to avoid this if possible as this is quite a lengthy process and isn’t really practical for me.

⚙️ What are my system specifications?

Software part of jetson-stats 4.3.0 - (c) 2024, Raffaello Bonghi
Model: Jetson AGX Orin - Jetpack 5.1 [L4T 35.2.1]
NV Power Mode[0]: MAXN
Serial Number: [XXX Show with: jetson_release -s XXX]
Hardware:
 - P-Number: p3701-0005
 - Module: NVIDIA Jetson AGX Orin (64GB ram)
Platform:
 - Distribution: Ubuntu 20.04 focal
 - Release: 5.10.104
jtop:
 - Version: 4.3.0
 - Service: Active
Libraries:
 - CUDA: 11.4.315
 - cuDNN: Not installed
 - TensorRT: Not installed
 - VPI: 2.2.4
 - OpenCV: 4.6.0-dev - with CUDA: YES

🤔 Conclusion

Is my hypothesis correct? Is the solution to try to enable the spi3 function in the jetson-io.py script? How do I go about doing this?

KevinFFF · April 9, 2025, 3:24am

Hi andrew.taylor,

Are you using the devkit or custom board for AGX Orin?

It seems you are using JP5.1(r35.2.1), could you move to the latest JP5.1.5(r35.6.1) or JP6.2(r36.4.3) to verify?

To verify SPI slave mode, you can refer to https://elinux.org/Jetson/L4T/peripheral/#Slave_Mode which has been verified on Orin Nano devkit.

spi3 does not present on 40-pins expansion header so that you can not use jetson-io script to configure it.
Alternatively, you can use pinmux spreadsheet to configure the pins to achieve similar effect for pinmux register.
e.g.

andrew.taylor · April 9, 2025, 7:50am

Hi @KevinFFF! 😄

Are you using the devkit or custom board for AGX Orin?

I’m using a devkit. 🧑‍💻

It seems you are using JP5.1(r35.2.1), could you move to the latest JP5.1.5(r35.6.1) or JP6.2(r36.6.3) to verify?

I can give it a try. What exactly are we looking to verify by doing this? 🔍

spi3 does not present on 40-pins expansion header so that you can not use jetson-io script to configure it.
Alternatively, you can use pinmux spreadsheet to configure the pins to achieve similar effect for pinmux register.
e.g.

What do you mean by this? Do you mean SPI3 doesn’t work on GPIO? What SPI devices present themselves on the 40-pin expansion header? 👋

Thanks so much for your help! ❤️

KevinFFF · April 10, 2025, 8:19am

Since you are using the devkit, you can simply update to the latest release in case you missed some fixes and we can work on the latest state.

No, I just mean that spi3 does not pinout from 40-pins expansion header so that it does not show in jetson-io tool.
(i.e. Jetson-IO tool is design to configure the pins from expansion header).
You can use the pins either as GPIO or SPI.
Please just configure them from pinmux spreadsheet before use.

andrew.taylor · April 10, 2025, 4:57pm

Hi @KevinFFF 😄

🚀 Upgrading the Jetson

I’ve upgraded the Jetson to r36.4.3.

Since upgrading the available SPI buses have changed. When I ran ls -la /dev/spi* I would see bus 0 and bus 2. When I run the same command on 36.4.3 I see bus 0 and bus 1 instead. 🚌

⚡ Flashing with Pinmux changes

🧑‍🔬 Pinmux spreadsheet

I’ve also attempted to flash the device with a custom version of the Pinmux. I downloaded the Orin Pinmux and made the following changes to SPI1 and SPI3.

SPI1:

SPI3:

🗄️ Copying the generated Pinmux files

I followed the instructions here to change the pinmux:

I placed the gpio dts file into <l4t_top>/bootloader/
I placed the pinmux dts file into <l4t_top>/bootloader/generic/BCT/.
I updated the p3701.conf.common file with the name of my pinmux dts file (Orin-jetson_agx_orin-pinmux.dtsi)
I then flashed the Orin with the following command: sudo ./tools/kernel_flash/l4t_initrd_flash.sh --external-device nvme0n1p1 \ -c tools/kernel_flash/flash_l4t_t234_nvme.xml \ --showlogs --network usb0 jetson-agx-orin-devkit external

🧪 Testing the SPI

After flashing was complete I ran sudo modprobe spidev . I then ran the following script with the spi loopback test binary as mentioned in my previous message:

sudo ./spidev_test -D /dev/spidev1.0 -s8000000 -g512 -b32 -H -p0 -n1 -r &
sleep 5
sudo ./spidev_test -D /dev/spidev0.0 -s8000000 -g512 -b32 -H -p0 -n1 -zzz -t

Which resulted in the following output:

/dev/spidev1.0: TEST FAILED !!!!! (status:-1)
Disabling receive
using device: /dev/spidev0.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 1
bits per word: 32 bytes per word: 4
max speed: 8000000 Hz (8000 KHz)
no. runs: 1
Using seed:0x67f7f651
loop count = 0
using sequential pattern ....
transfer bytes [512]
0000: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0010: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
0020: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
0030: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
0040: 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
0050: 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
0060: 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
0070: 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
0080: 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
0090: 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
00A0: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF
00B0: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
00C0: C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF
00D0: D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
00E0: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF
00F0: F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE 00
0100: 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
0110: 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
0120: 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
0130: 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
0140: 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
0150: 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60
0160: 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70
0170: 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80
0180: 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90
0190: 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0
01A0: A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0
01B0: B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0
01C0: C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0
01D0: D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0
01E0: E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0
01F0: F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE 00 01
/dev/spidev0.0: TEST PASSED
====== Transfer stats ====
Transmit:
       total: 512B (0KiB 0MiB)
       total: 1P
       ioerr: 0B (0KiB 0MiB)
       ioerr: 0P
 Rate:
  wire total: -1B/s (0KB/s)
       total: -1B/s (0KB/s)
  wire total: -1P/s
       total: -1P/s

  Total time: 0.001518s

After some further digging it seems that spidev1.0 behaves how spidev2.0 did on the previous version of the Jetson. The device is able to transmit data but cannot receive.

🔌 Wiring

For my test I had the following wiring configuration:

SPI1 MOSI (19) → SPI3 MOSI (37)
SPI1 CS0 (24) → SPI3 CS0 (18)

🎯 Troubleshooting

Do you know if I’ve misconfigured my pinmux? Could I have messed up the flashing process?

Thanks for your help! ❤️

KevinFFF · April 11, 2025, 8:42am

It should be fine, please just refer to the actual address for spi interface.
In your case, it should be 3210000 for SPI master, and 3230000 for SPI slave.
Have you also configured the compatible for 3230000 in device tree for SPI slave?

Please note that Int PD is invalid for Output pin, please configure Drive 0 instead.

These steps look good to me.

Please check the dmesg to confirm which SPI interface loaded earlier since the spi number here (spidev*.0) is assigned dynamically according to the order it probed.
Then you have to run SPI slave before SPI master.

Please also connect SPI1 MISO with SPI3 MISO before the test.

andrew.taylor · April 22, 2025, 10:08am

Hi @KevinFFF! Sorry for the delayed response. I wanted to update you since your last response.

🧑‍🔬 Updated Pinmux

I’ve updated the Pinmux as you suggested:

SPI1:

SPI3:

📒 `dmesg` output after modprobe spidev

Here’s what I could find for spi when running dmesg after running sudo modprobe spidev:

[    8.614511] spi-tegra114 3210000.spi: Adding to iommu group 1
[    8.641751] spi-tegra114 3230000.spi: Adding to iommu group 1

I’m assuming this gives the following assignment:

3210000 → spidev0.*
3230000 → spidev1.*

⚙️ SPI configuration

The following is the SPI configuration from the dts file created from kernel_tegra234-p3737-0000+p3701-0005-nv.dtb.

spi@3210000 {
        compatible = "nvidia,tegra210-spi\0nvidia,tegra114-spi";
        reg = &lt;0x00 0x3210000 0x00 0x1000&gt;;
        interrupts = &lt;0x00 0x24 0x04&gt;;
        #address-cells = &lt;0x01&gt;;
        #size-cells = &lt;0x00&gt;;
        clocks = &lt;0x03 0x87&gt;;
        assigned-clocks = &lt;0x03 0x87&gt;;
        assigned-clock-parents = &lt;0x03 0x66&gt;;
        clock-names = "spi";
        iommus = &lt;0x04 0x04&gt;;
        resets = &lt;0x03 0x5b&gt;;
        reset-names = "spi";
        dmas = &lt;0xee 0x0f 0xee 0x0f&gt;;
        dma-names = "rx\0tx";
        dma-coherent;
        status = "okay";

        prod-settings {
                #prod-cells = &lt;0x04&gt;;

                prod {
                        prod = &lt;0x00 0x194 0x80000000 0x00&gt;;

                        board {
                                prod = &lt;0x00 0x04 0x3f 0x30&gt;;
                        };
                };
        };

        spi@0 {
                compatible = "tegra-spidev";
                reg = &lt;0x00&gt;;
                spi-max-frequency = &lt;0x2faf080&gt;;
        };

        spi@1 {
                compatible = "tegra-spidev";
                reg = &lt;0x01&gt;;
                spi-max-frequency = &lt;0x2faf080&gt;;
        };
};

spi@3230000 {
        compatible = "nvidia,tegra210-spi\0nvidia,tegra114-spi";
        reg = &lt;0x00 0x3230000 0x00 0x1000&gt;;
        interrupts = &lt;0x00 0x26 0x04&gt;;
        #address-cells = &lt;0x01&gt;;
        #size-cells = &lt;0x00&gt;;
        clocks = &lt;0x03 0x89&gt;;
        clock-names = "spi";
        iommus = &lt;0x04 0x04&gt;;
        assigned-clocks = &lt;0x03 0x89&gt;;
        assigned-clock-parents = &lt;0x03 0x66&gt;;
        resets = &lt;0x03 0x5d&gt;;
        reset-names = "spi";
        dmas = &lt;0xee 0x11 0xee 0x11&gt;;
        dma-names = "rx\0tx";
        dma-coherent;
        status = "okay";

        prod-settings {
                #prod-cells = &lt;0x04&gt;;

                prod {
                        prod = &lt;0x00 0x194 0x80000000 0x00&gt;;

                        board {
                                prod = &lt;0x00 0x04 0x3f 0x20&gt;;
                        };
                };
        };

        spi@0 {
                compatible = "tegra-spidev";
                reg = &lt;0x00&gt;;
                spi-max-frequency = &lt;0x2faf080&gt;;
        };

        spi@1 {
                compatible = "tegra-spidev";
                reg = &lt;0x01&gt;;
                spi-max-frequency = &lt;0x2faf080&gt;;
        };
};

I’ve not made any changes to the configuration. Do I need to make changes to enable SPI slave on one of the devices? What changes should I make? Is this the correct file I should make changes to?

🔌 Updated wiring

The new wiring configuration is as follows:

SPI1 MOSI (19) → SPI3 MOSI (37)
SPI1 CS0 (24) → SPI3 CS0 (18)
SPI1 MISO (21) → SPI3 MISO (22)

📌 GPIO Pin clarification

I just wanted to double-check, are the following pins correct for SPI3?

MOSI - 37
MISO - 22
SCK - 13
CS0 - 18
CS1 - 16

🚦Current Status

After making the suggested Pinmux and wiring changes I ran the test again as before, however, I encountered the same failed result. In my test I made sure to run spidev1.0 before spidev0.1 as you mentioned previously.

Do you know if I’m missing anything with regards to the device tree? 🌲

Thanks again for your help! ❤️

andrew.taylor · April 22, 2025, 1:21pm

Hi @KevinFFF, I did a bit more digging since my last message.

🌲 Device Tree changes

In order to enable SPI 3230000 as a Slave device I’ve updated the device tree as so:

spi@3230000 {
        compatible = "nvidia,tegra210-spi-slave\0nvidia,tegra114-spi-slave";
        reg = &lt;0x00 0x3230000 0x00 0x1000&gt;;
        interrupts = &lt;0x00 0x26 0x04&gt;;
        #address-cells = &lt;0x01&gt;;
        #size-cells = &lt;0x00&gt;;
        clocks = &lt;0x03 0x89&gt;;
        clock-names = "spi";
        iommus = &lt;0x04 0x04&gt;;
        assigned-clocks = &lt;0x03 0x89&gt;;
        assigned-clock-parents = &lt;0x03 0x66&gt;;
        resets = &lt;0x03 0x5d&gt;;
        reset-names = "spi";
        dmas = &lt;0xee 0x11 0xee 0x11&gt;;
        dma-names = "rx\0tx";
        dma-coherent;
        status = "okay";

        prod-settings {
                #prod-cells = &lt;0x04&gt;;

                prod {
                        prod = &lt;0x00 0x194 0x80000000 0x00&gt;;

                        board {
                                prod = &lt;0x00 0x04 0x3f 0x20&gt;;
                        };
                };
        };

        spi@0 {
                compatible = "tegra-spidev";
                reg = &lt;0x00&gt;;
                spi-max-frequency = &lt;0x2faf080&gt;;
        };

        spi@1 {
                compatible = "tegra-spidev";
                reg = &lt;0x01&gt;;
                spi-max-frequency = &lt;0x2faf080&gt;;
        };
};

The only changes being made to the compatible attribute of spi@3230000.

📒 `dmesg` SPI output

After rebooting the system with the new device tree I recieved the following in the dmesg log.

[    9.828472] spi-tegra124-slave 3230000.spi: Adding to iommu group 1
[    9.828514] spi-tegra124-slave 3230000.spi: Dynamic bus number will be registered
[    9.841972] spi-tegra114 3210000.spi: Adding to iommu group 1

Given this I’ve assumed the following assignment:

spi@3230000 → spidev0.*
spi@3210000 → spidev1.*

🧪 Testing

After making the aforementioned changes, I decided to follow the test instructions here.

# Run in one terminal
sudo ./spidev_test -D /dev/spidev0.0 -s8000000 -g8 -b8 -H -f pattern.txt -n1 -zzz -r

# wait a few seconds

# Run in another terminal
sudo ./spidev_test -D /dev/spidev1.0 -s8000000 -g8 -b8 -H -f pattern.txt -n1 -zzz -t

📊 Results

Master

Disabling receive
using device: /dev/spidev1.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 1
bits per word: 8 bytes per word: 1
max speed: 8000000 Hz (8000 KHz)
no. runs: 1
Using seed:0x68079588
loop count = 0
Using user defined pattern from pattern.txt file ....
transfer bytes [8]
0000: 55 55 55 55 55 55 55 55
/dev/spidev1.0: TEST PASSED
====== Transfer stats ====
Transmit:
       total: 8B (0KiB 0MiB)
       total: 1P
       ioerr: 0B (0KiB 0MiB)
       ioerr: 0P
 Rate:
  wire total: -1B/s (0KB/s)
       total: -1B/s (0KB/s)
  wire total: -1P/s
       total: -1P/s

  Total time: 0.001079s

Slave

Disabling transmit
using device: /dev/spidev0.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 1
bits per word: 8 bytes per word: 1
max speed: 8000000 Hz (8000 KHz)
no. runs: 1
Using seed:0x68079582
loop count = 0
^Ctransfer ioctl error: -1
/dev/spidev0.0: TEST FAILED !!!!! (status:-1)
====== Transfer stats ====
Receive:
       total: 0B (0KiB 0MiB)
       total: 0P
        good: 0B (0KiB 0MiB)
        good: 0P
       ioerr: 1P
     dataerr: 0P
 Rate:
        good: 0B/s (0KB/s)
        good: 0P/s
 packet drop: -1/10000

  Total time: 7.501527s

The behaviour of the slave is slightly different now in that when I run it as mentioned, it waits. Previously, when I would run the slave, it would immediately fail.

In addition, I get the following messages in dmesg each time I run the test:

[  211.644745] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[  211.644814] spi_master spi0: failed to transfer one message from queue
[  266.955377] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[  266.955431] spi_master spi0: failed to transfer one message from queue
[  322.632522] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[  322.632587] spi_master spi0: failed to transfer one message from queue
[  327.176292] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[  327.176352] spi_master spi0: failed to transfer one message from queue
[  455.640039] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[  455.640080] spi_master spi0: failed to transfer one message from queue
[  509.505682] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[  509.505732] spi_master spi0: failed to transfer one message from queue
[  789.452105] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[  789.452144] spi_master spi0: failed to transfer one message from queue
[  859.728310] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[  859.728353] spi_master spi0: failed to transfer one message from queue
[  973.179931] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[  973.179990] spi_master spi0: failed to transfer one message from queue
[ 3162.299813] spi-tegra124-slave 3230000.spi: waiting for controller was interrupted
[ 3162.299845] spi_master spi0: failed to transfer one message from queue

🤔 What next?

Do you have any ideas of what could be wrong? It looks like my problems might be similar to those here.

KevinFFF · April 23, 2025, 7:25am

Please also connect the pin for SPI clock.

SPI1 SCK(23) -> SPI3 SCK (13)

Correct!

Yes, your modification is expected/required to configure SPI3 as SPI slave.

It is caused from that you didn’t configure it as SPI slave before.

Your current test steps look good to me.
Please connect SPI SCK between SPI1 and SPI3 and verify again.

andrew.taylor · April 23, 2025, 7:54am

Hi @KevinFFF. 😄

🔌 Updated wiring config

SPI1 MOSI (19) → SPI3 MOSI (37)
SPI1 CS0 (24) → SPI3 CS0 (18)
SPI1 MISO (21) → SPI3 MISO (22)
SPI1 SCK (23) → SPI3 SCK (13)

In addition here’s an image of the physical connections:

✅ Master output verification

I’ve also checked the output of the Master SPI using a logic analyser and it all seems to be correct in terms of the MOSI, CS, and SCK lines.

🚦 Current Status

Unfortunately, I’m still getting the same outcome. The Master transmits data successfully but the Slave doesn’t receive anything and when I terminate the Slave’s process I get TEST FAILED.

Thanks for your help! ❤️

andrew.taylor · April 25, 2025, 6:58am

Hi @KevinFFF! 😄

I’ve been doing a little bit more digging since my last message around other SPI issues. I found this post here which mentions issues with the actual spidev_test binary. In the post the author uses an older spidev_test binary to begin with which only works on a certain Jetpack version. The author then goes on to edit the spidev_test.c found at the linux repository which eventually works. 🚀

I’ve been using the spidev_test binary linked by one of your colleagues in a much older post here. Given the author of that forum post was working on a Xavier I can imagine this was also for a much older Jetpack version. 🦖

Would you be able to send me the latest version of the spidev_test binary for Jetpack r36.4.3 so I can rule this out?

Thanks for your help! ❤️

ShaneCCC · April 25, 2025, 7:17am

Can you verify the binary for current release.

andrew.taylor · April 25, 2025, 7:25am

Hi @ShaneCCC! 😄

What do you mean by this? Do you mean run the tests with the older binary? If so, I’ve already done this and it doesn’t work. That’s what the results here are from, the only difference being that the slave doesn’t crash instantly now that its marked as a slave.

ShaneCCC · April 25, 2025, 7:38am

Ok, I didn’t follow the whole discussion thread.
Here’s the binary build from JP6 release base.

spidev_test (103.4 KB)

andrew.taylor · April 25, 2025, 7:54am

Hi @ShaneCCC, 😄

Thanks for sending the new binary over. 📬

🧪 Test with new binary

I’ve just run the following test with the new binary:

sudo ./nv_spidev_test_jp_6 -D /dev/spidev1.0 -s8000000 -g512 -b32 -H -p0 -n1 -r -zzz

# Wait 5 seconds-ish

sudo ./nv_spidev_test_jp_6 -D /dev/spidev0.0 -s8000000 -g512 -b32 -H -p0 -n1 -zzz -t

📊 Results

Master

Disabling receive
using device: /dev/spidev0.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 1
bits per word: 32 bytes per word: 4
max speed: 8000000 Hz (8000 KHz)
no. runs: 1
Using seed:0x680b3ef6
loop count = 0
using sequential pattern ....
transfer bytes [512]
0000: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0010: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
0020: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
0030: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
0040: 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
0050: 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
0060: 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
0070: 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
0080: 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
0090: 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
00A0: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF
00B0: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
00C0: C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF
00D0: D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
00E0: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF
00F0: F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE 00
0100: 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
0110: 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
0120: 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
0130: 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
0140: 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
0150: 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60
0160: 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70
0170: 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80
0180: 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90
0190: 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0
01A0: A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0
01B0: B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0
01C0: C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0
01D0: D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0
01E0: E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0
01F0: F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE 00 01
/dev/spidev0.0: TEST PASSED
====== Transfer stats ====
Transmit:
       total: 512B (0KiB 0MiB)
       total: 1P
       ioerr: 0B (0KiB 0MiB)
       ioerr: 0P
 Rate:
  wire total: -1B/s (0KB/s)
       total: -1B/s (0KB/s)
  wire total: -1P/s
       total: -1P/s

  Total time: 0.001125s

Slave

using device: /dev/spidev1.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 1
bits per word: 32 bytes per word: 4
max speed: 8000000 Hz (8000 KHz)
no. runs: 1
Using seed:0x680b3ef0
loop count = 0
^Ctransfer ioctl error: -1
/dev/spidev1.0: TEST FAILED !!!!! (status:-1)
====== Transfer stats ====
Receive:
       total: 0B (0KiB 0MiB)
       total: 0P
        good: 0B (0KiB 0MiB)
        good: 0P
       ioerr: 1P
     dataerr: 0P
 Rate:
        good: 0B/s (0KB/s)
        good: 0P/s
 packet drop: -1/10000

  Total time: 8.336675s

Do you have any ideas on what I should try next?

KevinFFF · April 25, 2025, 8:42am

I just notice that you are using AGX Orin devkit rather than Orin Nano devkit.
As a result, the PIN37/PIN18/PIN22/PIN13 are not the pins for SPI3.
For AGX Orin, you should refer to the following figure for the pins used on 40-pins header.

There seems only one SPI interface available on 40-pins header.
Do you have another devkit so that you can use one as SPI master and another as SPI slave?

andrew.taylor · April 25, 2025, 8:56am

Hi @KevinFFF, 😄

Does this mean that the AGX Orin devkit doesn’t support more than one SPI on its GPIO? The set up I was aiming to implement was to loop the first SPI back into the second SPI on the same device. 🔄 Would this only be possible on a Nano?

Thanks! ❤️

ShaneCCC · April 28, 2025, 1:38am

You may reference to below topic to enable the CAM_SPI for another SPI controller.

andrew.taylor · April 28, 2025, 7:35am

Hi @ShaneCCC! 👋

Thanks for getting back to me. I’ve had a read through that post and I’ll give it a try. I just wanted to clarify a couple of things:

🚦 Will utilising the CAM SPI pins work on the Orin? The post you sent over was for the Xavier originally.
🔌 Do you know what pins the CAM SPI correspond to on the Orin?
⚙️ Is it possible to configure the CAM SPI as a Slave and have SPI 1 as a Master?

Thanks again for your help! ❤️

ShaneCCC · April 28, 2025, 8:59am

Suppose it could be the same with Xavier.
Below is from pinmux file.

SPI2_CLK	SPI2_SCK	GP06_SPI2_CLK	50k	pd	GPIO3_PCC.00	Input	Int PU		Initiator	Disable	Disable	Camera connector interrupt 1	GPIO: CAM_INT1
SPI2_MISO	SPI2_MISO	GP07_SPI2_MISO	50k	pd	GPIO3_PCC.01	Input	Int PU		Initiator	Disable	Disable	Camera connector interrupt 2	GPIO: CAM_INT2
SPI2_MOSI	SPI2_MOSI	GP08_SPI2_MOSI	50k	pd	GPIO3_PCC.02	Input	Int PU		Initiator	Disable	Disable	Camera connector interrupt 3	GPIO: CAM_INT3
SPI2_CS0_N	SPI2_CS0	GP09_SPI2_CS_N	50k	z	GPIO3_PCC.03	Input	Int PU	Yes	Initiator	Disable	Disable	Camera connector interrupt 4	GPIO: CAM_INT4

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Unable to get SPI Master and Slave devices on Jetson GPIO

⛓️‍💥 What is the problem?

🧪 My hypothesis

🛠️ What have I tried?

⚙️ What are my system specifications?

🤔 Conclusion

🚀 Upgrading the Jetson

⚡ Flashing with Pinmux changes

🧑‍🔬 Pinmux spreadsheet

🗄️ Copying the generated Pinmux files

🧪 Testing the SPI

🎯 Troubleshooting

🧑‍🔬 Updated Pinmux

📒 dmesg output after modprobe spidev

⚙️ SPI configuration

🔌 Updated wiring

📌 GPIO Pin clarification

🚦Current Status

🌲 Device Tree changes

📒 dmesg SPI output

🧪 Testing

📊 Results

🤔 What next?

🔌 Updated wiring config

✅ Master output verification

🚦 Current Status

🧪 Test with new binary

📊 Results

Related topics

📒 `dmesg` output after modprobe spidev

📒 `dmesg` SPI output