Hi,
I am designing a carrier board for the AGX Orin. In Nvidia’s reference carrier board schematic, the RX9 lane of the PCIe x16 slot is labeled as “xfi1_mdc_con”. As far as I know, this pin should normally be a PCIe data lane, but here it appears to be assigned as an XFI (10G Ethernet) management signal (mdc).
Is this usage intentional in the reference design? At first, I thought there was some multiplexing between PCIe and XFI, but the signal seems to come directly from the module through a voltage-level translator to the PCIe x16 RX9 lane. Does the function of this pin change via firmware or hardware configuration? Could you please provide more technical details or documentation about this implementation?
Thank you!