Disable Spread Spectrum (SSC) on the TX1 with a 28.1 release

Autonomous Machines Jetson & Embedded Systems Jetson TX1
#1

Hi,

I have migrated from a 24.2.1 release (kernel 3.19) to a 28.1 on a TX1. However, we need to have spread spectrum disabled on our custom board. On the 3.19 kernel we had to set USE_PLLE_SS 0 in clock.h and tegra_cl_dvfs.h in order to disable SSC. This no longer works for kernel 4.4 (r28.1). Is there an alternative way to disable SCC for the TX1 (not TX2) when r28.1 is used. Thanks in advance.

#2
  1. Try to use dtc to un-compile Linux_for_Tegra_tx2/bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-c01-00-te770d-ucm2.dtb by below command.

“dtc -I dtb -O dts -o tx2-bpmp.dtsi tegra186-a02-bpmp-quill-p3310-1000-c01-00-te770d-ucm2.dtb”

  1. add below to the tx2-bpmp.dtsi in the clocks scope

“dtc -I dts -O dtb -o tegra186-a02-bpmp-quill-p3310-1000-c01-00-te770d-ucm2.dtb tx2-bpmp.dtsi”

  1. replace the original tegra186-a02-bpmp-quill-p3310-1000-c01-00-te770d-ucm2.dtb tx2-bpmp.dtsi at …/Linux_for_Tegra_tx2/bootloader/t186ref

  2. sudo ./flash -r -k bpmp-fw-dtb jetson-tx2 mmcblk0p1

clock@plle {
                        clk-id = <0x200>;
                        pll_freq_table = <0x249f000 0x5f5e100 0x2 0x7d 0x18 0xffffffff 0xffffffff 0xffffffff 0xffffffff>;
                };
Tegra NX PCIe Reference Clock Design
#3

hi ShaneCCC,

thanks for the quick response. The files you refer to, are TX2 related. I am using a TX1 and those files do not exist. For instance, I have the following path: Linux_for_Tegra_64_tx1/bootloader/t210ref/ and there are no dtb files there. Do you imply that I should un-compile a TX2 dtb and use it on a TX1 installation? Thanks again.

#4

@piperak
Please try this patch

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index b05221e34f60..faea58803092 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -2215,7 +2215,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)

     if (ret < 0)
         goto out;
-
+#if 0
     val = pll_readl(PLLE_SS_CTRL, pll);
     val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
     val &= ~PLLE_SS_COEFFICIENTS_MASK;
@@ -2227,7 +2227,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
     val &= ~PLLE_SS_CNTL_INTERP_RESET;
     pll_writel(val, PLLE_SS_CTRL, pll);
     udelay(1);
-
+#endif
 out:
     if (pll->lock)
         spin_unlock_irqrestore(pll->lock, flags);
#5

Hi ShaneCCC,

yes I had tried that and it works, but I was hopping if there was a way to disable SSC through the device tree. Thanks anyway.

#6

@piperak
Did you try my early comment to modify the bpmb DT?

#7

@ShaneCCC
I have done as u said,but when i burn the board,a mistake is occur. like this:
[ 5.0050 ] tegrarcm_v2 --isapplet
[ 5.6726 ]
[ 5.6974 ] tegradevflash_v2 --iscpubl
[ 5.7002 ] CPU Bootloader is not running on device.
[ 5.7053 ]
[ 6.9959 ] Writing partition
[ 6.9982 ] tegradevflash_v2 --write bpmp-fw-dtb /home/Linux_for_Tegra/bootloader/t186ref/signed/tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2_sigheader.dtb.encrypt
[ 7.0001 ] Bootloader version 01.00.0000
[ 7.0048 ] File to be written cannot be of zero size
[ 7.0048 ]
Error: Return value 10
Command tegradevflash_v2 --write bpmp-fw-dtb /home/Linux_for_Tegra/bootloader/t186ref/signed/tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2_sigheader.dtb.encrypt
Failed to flash/read t186ref.

what’is wrong?

#8

Could you clarify below command without modify the dtb file?

sudo ./flash -r -k bpmp-fw-dtb jetson-tx2 mmcblk0p1
#9

i did not modify it but it is report error to

#10

Just recall bpmp is for TX2 only.
I would suggest you to implement the clk-pll.c to parser the DT to disable it.

#11

can i disable it like tx1 as you mention in 4#

#12

Does 101534645 the same with piperak?

Does #4 already confirm worked?

#13

my board is TX2 and i connected a idt bridge to pcie x4, i need to close ssc.
now,i change clk-pll.c as #4.
but my kernel also report error like this:
[ 41.108106] pcieport 0000:00:01.0: can’t find device of ID0020
[ 41.111947] pcieport 0000:00:01.0: AER: Multiple Corrected error received: id=0020
[ 41.112280] pcieport 0000:00:01.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, id=0008(Receiver ID)
[ 41.112281] pcieport 0000:00:01.0: device [10de:10e5] error status/mask=00000081/00002000
[ 41.112283] pcieport 0000:00:01.0: [ 0] Receiver Error (First)
[ 41.112284] pcieport 0000:00:01.0: [ 7] Bad DLLP
[ 41.112291] pcieport 0000:00:01.0: AER: Multiple Corrected error received: id=0020

i need you help to Analysis this problem

#14

can this patch be used for tx2 ??

#15

how do i confirm that ssc is disabled after flashing the updated tegra186-a02-bpmp-quill-p3310-1000-c01-00-te770d-ucm2.dtb ??

#16

In CAR module, the following register can be checked to find out if SSC is enabled or not.
CLK_RST_CONTROLLER_PLLE_SS_CNTL_0
is the register and PLLE_SSCBYP is the field.
If it is ‘0’ - SSC is enabled
‘1’ - SSC is disabled

-reg addr 0x60006068
0x60006068: CLK_RST_CONTROLLER_PLLE_SS_CNTL_0                       = 0x00005c00 //
          PLLE_INTEGOFFSET                                        = 0x00000000 // [31:30]=        0
          PLLE_SSCINCINTRV                                        = 0x00000000 // [29:24]=        0
          PLLE_SSCINC                                             = 0x00000000 // [23:16]=        0
          PLLE_SSCINVERT                                          = 0x00000000 // [15:15]=        0
          PLLE_SSCCENTER                                          = 0x00000001 // [14:14]=        1
          PLLE_SSCPDMBYP                                          = 0x00000000 // [13:13]=        0
          PLLE_SSCBYP                                             = 0x00000001 // [12:12]=        1
          PLLE_INTERP_RESET                                       = 0x00000001 // [11:11]=        1
          PLLE_BYPASS_SS                                          = 0x00000001 // [10:10]=        1
          PLLE_SSCMAX                                             = 0x00000000 // [08:00]=        0