Questions about PCB trace

[chiaueng]

We would like to ask some PCB trace requirement question, accroding to the “Jetson_AGX_Orin_Series_Design_Guide_DG-10653-001_v14.pdf” chapter 10.2 describe the CSI C-PHY design guildelines,

1.) what is the reason limit the PCB trace length in NV MIPI RX? such as some design limitation usually on MIPI TX side, the driving strength is not enough to drive top long PCB trace.

2.) if our FPGA C-PHY have some driving strength enhance circuit to enlarge the signal, let the MDI signal on the NV MIPI RX PIN is better, whether can have more length than the design guildeline?

Jetson_AGX_Orin_Series_Design_Guide_DG-10653-001_v14 1.pdf (3.5 MB)

[sgursal]

Max trace length is based on the assumptions in the Notes and higher the frequencies higher the insertion loss in PCB traces, hence shorter trace lengths requirements/limits in the design guide. If your FPGA supports higher drive swing to overcome trace losses then you will need to do signal integrity simulation and also test/validate it to verify that it meets your requirements.