Let me ask a question regarding to the item of “Max trace delay skew between DQ and CLK” in 7.1.1 MIPI DSI and CSI Design Guidelines. The requirement of this is 5ps.
But As for the MIPI D-phy specification (v1.2), the data to clock skew at RX is +/-0.20 UI.
Bit rate of the data of our application is 2Gbps. Then 0.20 UI is about 100ps, so the 5ps requirement is far strict.
I’d like to add some comment and add questions.
There is similar post regarding the MIPI CSI skew.
And this post ended by NVidia side answer “This skew is for PCB, in fact there is other skew in chip. The total skews are following D-PHY request.”
Let me ask the further question.
What is this “the skew for PCB”? Does this PCB mean carier board?
What does “other skew in chip” mean?
And it describes “The total skews are following D-PHY request.”
As for the specification of MIPI D-PHY, Dynamic Data to Clock Skew Window RX Tolerance is 0.5UI. The timing budget is 0.5UI in total.
So if this window is kept, is it OK (Jetson can receives MIPI CSI data) even if this trace delay skew between DQ and CLK is more than 5ps
(this means other skews are controlled small enough)?
Thank you for reply, but sorry, this answer is not enough.
As I wrote the window tolerant is 0.5UI and timing budget is much enough compared to this 5ps specification.
This 5ps specification seems that the trace length differences between all the DQ lines shall be less than 0.75mm,
and for achieving this large area of PCB is needed for serpentine traces. This is difficult for small carrier board.
Is the aim of this 5ps the trace layout of almost the same length of DQs?
Or if this 5 psec is one of the skew factors to be considered within the timing budget
when calculating according to the MIPI D-PHY specification, then I understand.
For DPHY only application you can use +/-0.1UI (40ps). 5ps skew between DQ and CLK requirement is for application supporting both CPHY and DPHY in the same PCB design.
