Let me ask a question regarding to the item of “Max trace delay skew between DQ and CLK” in 7.1.1 MIPI DSI and CSI Design Guidelines. The requirement of this is 5ps.
But As for the MIPI D-phy specification (v1.2), the data to clock skew at RX is +/-0.20 UI.
Bit rate of the data of our application is 2Gbps. Then 0.20 UI is about 100ps, so the 5ps requirement is far strict.
I’d like to add some comment and add questions.
There is similar post regarding the MIPI CSI skew.
And this post ended by NVidia side answer “This skew is for PCB, in fact there is other skew in chip. The total skews are following D-PHY request.”
Let me ask the further question.
What is this “the skew for PCB”? Does this PCB mean carier board?
What does “other skew in chip” mean?
And it describes “The total skews are following D-PHY request.”
As for the specification of MIPI D-PHY, Dynamic Data to Clock Skew Window RX Tolerance is 0.5UI. The timing budget is 0.5UI in total.
So if this window is kept, is it OK (Jetson can receives MIPI CSI data) even if this trace delay skew between DQ and CLK is more than 5ps
(this means other skews are controlled small enough)?
Thank you for reply, but sorry, this answer is not enough.
As I wrote the window tolerant is 0.5UI and timing budget is much enough compared to this 5ps specification.
This 5ps specification seems that the trace length differences between all the DQ lines shall be less than 0.75mm,
and for achieving this large area of PCB is needed for serpentine traces. This is difficult for small carrier board.
Is the aim of this 5ps the trace layout of almost the same length of DQs?
Or if this 5 psec is one of the skew factors to be considered within the timing budget
when calculating according to the MIPI D-PHY specification, then I understand.
For DPHY only application you can use +/-0.1UI (40ps). 5ps skew between DQ and CLK requirement is for application supporting both CPHY and DPHY in the same PCB design.
It seems a new specifications(figures) have come out.
Is this +/-0.1UI figures (only for MIPI D-PHY) shown somewhere?
And you mention C-PHY and D-PHY traces,
C-PHY protocol is different from D-PHY, C-PHY 1 lane consists of 3 pair,
and C-PHY does not exist clock lane, as you know,
so both C-PHY and D-PHY support in the same PCB is unrealistic.
And this parameter is "max trace delay skew between “DQ and CLK” " so it’s so hard to apply this 5ps requirement to C-PHY.
Please check our other carrier board reference designs and the corresponding design guides. We do support CPHY and DPHY in same PCB. For example, Jetson AGX Orin.
Clarification will be added in future design guide update.
As I check the Jetson_AGX_Orin_Series_Design_Guide, it is shown that
in the case of D-PHY,
“Max Trace Delay Skew between DQ and CLK” is 16ps when the bit rate is 2.5Gbps,
and
"Max Inter-Trio Skew (between Trios) is 55ps, for example
the difference between trace length of {HS_CSI0_D0_N, HS_CSI0_D0_P, HS_CSI0_CLK_P} and {HS_CSI0_D1_N, HS_CSI0_D1_P, HS_CSI0_CLK_N} permits 55ps.
These specification seems loser than the specification of “Max trace delay skew between DQ and CLK 5ps” you mentioned
even considering “for application supporting both CPHY and DPHY in the same PCB design”
To begin with, the TX2 NX doesn’t support MIPI C-PHY, the 5ps specification doesn’t seem realistic.
Therefore I wish the specification update of Jetson TX2 NX and I’ll wait for it.
